AD9806 查看數據表（PDF） - Analog Devices

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AD9806

Complete 10-Bit 18 MSPS CCD Signal Processor

Analog Devices 

SERIAL INTERFACE SPECIFICATIONS

SDATA

A0

A1

A2

D0

D1

D2

D3

D4

D5

D6

D7

SELECT

MODES

1

PGA

0

0

0

1

0

e0

e1

CLAMP

LEVEL

f0

f1

d0

d1

POWER-DOWN

MODES

f2

f3

c0

c1

CLOCK

MODES

f4

f5

b0

b1

OUTPUT

MODES

f6

f7

PGA GAIN LEVEL SELECTION

g0

g1

g2

g3

g4

g5

g6

g7

DAC1

1

1

0

DAC1 INPUT

DAC2

0

0

MODES21

1

1

h0

h1

h2

h3

h4

h5

h6

h7

1

DAC2 INPUT

m0

0*

DON'T

CARE

j0

1

OPERATION AND

POWER-DOWN MODES

AD9806

D8

D9

a0

a1

OPERATION

MODES

f8

f9

SELECT

SHIFT REGISTER

a0–a1

A-REG

b0–b1

B-REG

c0–c1

C-REG

d0–d1

D-REG

e0–e1

E-REG

f0–f9

F-REG

(a) OPERATION MODES

g0–g7

G-REG

(b) OUTPUT MODES

h0–h7

H-REG

(c) CLOCK MODES

j0

J-REG

(d) POWER-DOWN MODES

(e) CLAMP LEVEL

(f) PGA GAIN

m0

M-REG

(g) DAC1 INPUT

(h) DAC2 INPUT

(j) EVEN-ODD OFFSET

CORRECTION

*NOTE: MODES2 REGISTER BIT D1 MUST BE SET TO ZERO

Figure 7. AD9806 Internal Register Map

(m) DAC1 AND DAC2

POWER-DOWN

REV. 0

SDATA

SCK

SL

RNW

A0 A1 A2 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

RISING EDGE

TRIGGERED

tDH

tDS

tLS

tLH

REGISTER LOADED ON

RISING EDGE

Figure 8. Serial WRITE Operation

DUMMY BITS

IGNORED

RNW

SDATA

A0 A1 A2 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 XX XX

SCK

SL

Figure 9. 16-Bit Serial WRITE Operation

–9–

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