AD9821 查看數據表（PDF） - Analog Devices

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AD9821

Complete 12-Bit 40 MSPS Imaging Signal Processor

Analog Devices 

AD9821

IMAGER MODE AND AUX MODE TIMING

VIN+

VIN–

DATACLK

OUTPUT

DATA

N

tID

N+1

N+2

tCONV

tOD

N–10

tH

N–9

N–8

N+9

N+8

N–1

N

NOTES:

1. VIN+ AND VIN– SIGNALS ARE SAMPLED AT DATACLK RISING EDGES (CAN BE INVERTED USING THE CONTROL REGISTER).

2. INTERNAL SAMPLING DELAY (APERTURE) tID IS TYPICALLY 3 ns.

3. OUTPUT DATA LATENCY IS NINE DATACLK CYCLES.

Figure 5. Imager Mode Timing

EFFECTIVE PIXELS

OPTICAL BLACK PIXELS

HORIZONTAL

BLANKING

EFFECTIVE PIXELS

IMAGER

SIGNAL

CLPOB

PBLK

OUTPUT

DATA

EFFECTIVE PIXEL DATA

OB PIXEL DATA

EFFECTIVE DATA

NOTES:

1. CLPOB WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING CLPOB.

2. PBLK SIGNAL IS OPTIONAL.

3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS NINE DATACLK CYCLES.

Figure 6. Typical Imager Mode Line Clamp Timing

–8–

REV. 0

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