AD9821KST 查看數據表（PDF） - Analog Devices
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AD9821KST Datasheet PDF : 16 Pages
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AD9821
INTERNAL REGISTER MAP AND SERIAL INTERFACE TIMING
Table I. Internal Register Map
Register
Name
Operation
Address
A0 A1 A2
000
D0 D1 D2
Input Mode
Selection
Data Bits
D3 D4 D5
D6
Power-Down
Modes
Software OB Clamp
Reset On/Off
D7 D8 D9
01
12
01
VGA Gain 1 0 0
LSB
Clamp Level 0 1 0
Control
110
LSB
01
01
01
01
01
MSB X
Clock Polarity Select for 01
01
CLP/DATA
NOTES
1Internal use only. Must be set to 0.
2Must be set to 1.
D10
01
01
MSB X
X
X
01
X
SDATA
tDS
SCK
RNW
TEST BIT
0
A0
A1
A2
0
D0
D1
D2
D3
D4 D5
D6
D7
tDH
D8 D9 D10
tLS
tLH
SL
NOTES:
1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK.
2. RNW = READ-NOT WRITE. SET LOW FOR WRITE OPERATION.
3. TEST BITS = INTERNAL USE ONLY. MUST BE SET LOW.
4. SYSTEM UPDATE OF LOADED REGISTERS OCCURS ON SL RISING EDGE.
Figure 7. Serial Write Operation
SDATA
RNW
TEST BIT
1
A0
A1
0
0
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
tDS
tDH
tDV
SCK
tLS
tLH
SL
NOTES:
1. RNW = READ-NOT WRITE. SET HIGH FOR READ OPERATION.
2. TEST BITS = INTERNAL USE ONLY. MUST BE SET LOW.
3. SERIAL DATA FROM THE SELECTED REGISTER IS VALID STARTING AFTER THE FIFTH SCK FALLING EDGE, AND IS UPDATED ON
SCK FALLING EDGES.
Figure 8. Serial Readback Operation
SDATA
RNW A0 A1 A2
11 BITS
OPERATION
10 BITS
VGA GAIN
8 BITS
CLAMP LEVEL
10 BITS
CONTROL
0 0 0 0 0 D0 D1 D2 D3 ... D10 D0 D1 D2 D3 ... D9 D0 D1 D2 D3 ... D7 D0 D1 D2 D3 ... D9
SCK
...
...
...
...
1 2 3 4 5 6 78 9
16 17 18 19 20
26 27 28 29 30
34 35 36 37 38
44
SL
...
NOTES:
1. ANY NUMBER OF ADJACENT REGISTERS MAY BE LOADED SEQUENTIALLY, BEGINNING WITH THE LOWEST ADDRESS AND INCREMENTING ONE ADDRESS AT A TIME.
2. WHEN SEQUENTIALLY LOADING MULTIPLE REGISTERS, THE EXACT REGISTER LENGTH (SHOWN ABOVE) MUST BE USED FOR EACH REGISTER.
3. ALL LOADED REGISTERS WILL BE SIMULTANEOUSLY UPDATED WITH THE RISING EDGE OF SL.
Figure 9. Continuous Serial Write Operation to All Registers
REV. 0
–9–
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