AD9826 查看數據表（PDF） - Analog Devices

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AD9826

Complete 16-Bit Imaging Signal Processor

Analog Devices 

AD9826

ANALOG

INPUTS

CDSCLK2

PIXEL n (R,G,B)

tAD

tC2

tC2AD

PIXEL (n+1)

tPRA

ADCCLK

tADCLK

tADC2

tC2ADR

OUTPUT

DATA

D<7:0>

tADCLK

tOD

R (n–2) G (n–2) G (n–2) B (n–2) B (n–2) R (n–1) R (n–1) G (n–1) G (n–1) B (n–1) B (n–1) R (n) R (n) G (n) G (n)

HIGH LOW

HB

LB

HB

LB

HB

LB

HB

LB

HB

LB

HB

LB

BYTE BYTE

Figure 5. 3-Channel SHA Mode Timing

ANALOG

INPUTS

CDSCLK2

ADCCLK

OUTPUT

DATA

D<7:0>

PIXEL n

tAD

tC2

tPRB

tC2ADR

tC2ADF

ttAADDCCLLKK

tADCLK

tOD

PIXEL (n–4)

PIXEL (n–4)

PIXEL (n–3)

PIXEL (n–3)

PIXEL (n–2)

HIGH BYTE

LOW BYTE

HIGH BYTE

LOW BYTE

HIGH BYTE

NOTE

IN 1-CHANNEL SHA MODE, THE CDSCLK2 RISING EDGE MUST OCCUR WHILE ADCCLK IS “LOW.”

Figure 6. 1-Channel SHA Mode Timing

PIXEL (n–2)

LOW BYTE

–10–

REV. B

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