AD9826 查看數據表（PDF） - Analog Devices

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AD9826

Complete 16-Bit Imaging Signal Processor

Analog Devices 

AD9826

TIMING DIAGRAMS

ANALOG

INPUTS

tAD

tC1

PIXEL n (R,G,B)

tAD

tC2C1

PIXEL

(n+1)

tPRA

PIXEL

(n+2)

CDSCLK1

CDSCLK2

tC1C2

tC2

tC2ADF

ADCCLK

tADCLK

tADC2

tC2ADR

OUTPUT

DATA

D<7:0>

tADCLK

tOD

R(n–2) G(n–2) G(n–2) B(n–2) B(n–2) R(n–1) R(n–1) G(n–1) G(n–1) B(n–1) B(n–1) R(n)

HIGH LOW

HB

LB

HB

LB

HB

LB

HB

BYTE BYTE

LB

HB

R(n)

LB

G(n) G(n)

HB

LB

Figure 1. 3-Channel CDS Mode Timing

It is recommended that CDSCLK falling edges do not occur within the first 10 ns following an ADCCLK edge.

ANALOG

INPUTS

CDSCLK1

CDSCLK2

ADCCLK

OUTPUT

DATA

D<7:0>

tAD

tC1

PIXEL n

tAD

tC2C1

PIXEL

(n+1)

tPRB

PIXEL

(n+2)

tC1C2

tC2

tC2ADR

tC2ADF

tADCLK

tADCLK

tOD

PIXEL (n–4)

PIXEL (n–4)

PIXEL (n–3)

PIXEL (n–3)

PIXEL (n–2)

PIXEL (n–2)

HIGH BYTE

LOW BYTE

HIGH BYTE

LOW BYTE

HIGH BYTE

LOW BYTE

NOTE

IN 1-CHANNEL CDS MODE, THE CDSCLK1 FALLING EDGE AND THE CDSCLK2 RISING EDGE MUST OCCUR WHILE ADCCLK IS “LOW.”

Figure 2. 1-Channel CDS Mode Timing

–8–

REV. B

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