AD9838 查看數據表（PDF） - Analog Devices
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AD9838 Datasheet PDF : 32 Pages
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AD9838
The prominence of the aliased images depends on the ratio of
fOUT to MCLK. If the ratio is small, the aliased images are very
prominent and of a relatively high energy level as determined by
the sin(x)/x roll-off of the quantized DAC output. In fact, depend-
ing on the fOUT/reference clock ratio, the first aliased image can
be on the order of −3 dB below the fundamental.
A low-pass filter is generally placed between the output of the
DAC and the input of the comparator to further suppress the
effects of aliased images. To avoid unwanted (and unexpected)
output anomalies, it is necessary to consider the relationship of
the selected output frequency and the reference clock frequency.
To apply the AD9838 as a clock generator, limit the selected
output frequency to <33% of the reference clock frequency. In
this way, the user can prevent the generation of aliased signals
that fall within, or close to, the output band of interest (generally
the dc selected output frequency). This practice reduces the
complexity (and cost) of the external filter requirement for the
clock generator application. For more information, see the
AN-837 Application Note.
To enable the comparator, the SIGN/PIB and OPBITEN bits in
the control resister must be set to 1 (see Table 18).
REGULATOR
The AD9838 has separate power supplies for the analog and
digital sections. AVDD provides the power supply required for
the analog section, and DVDD provides the power supply for
the digital section. Both supplies can have a value of 2.3 V to
5.5 V and are independent of each other. For example, the
analog section can be operated at 5 V, and the digital section
can be operated at 3 V, or vice versa.
The internal digital section of the AD9838 is operated at 2.5 V.
An on-board regulator steps down the voltage applied at DVDD
to 2.5 V. The digital interface (serial port) of the AD9838 also
operates from DVDD. These digital signals are level shifted
within the AD9838 to make them 2.5 V compatible.
If the voltage applied at the DVDD pin of the AD9838 is less than
or equal to 2.7 V, the CAP/2.5V and DVDD pins should be tied
together to bypass the on-board regulator.
fOUT
sin(x)/x ENVELOPE
x = π (f/fC)
fC – fOUT
fC + fOUT
fC
2fC – fOUT
2fC + fOUT
2fC
3fC – fOUT
3fC 3fC + fOUT
0Hz
FIRST
SECOND
THIRD
FOURTH
FIFTH
SIXTH
IMAGE
IMAGE
IMAGE
IMAGE
IMAGE
IMAGE
SYSTEM CLOCK
FREQUENCY (Hz)
Figure 21. DAC Output Spectrum
Rev. A | Page 16 of 32
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