AD9838 查看數據表（PDF） - Analog Devices
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AD9838 Datasheet PDF : 32 Pages
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FREQUENCY AND PHASE REGISTERS
The AD9838 contains two frequency registers and two phase
registers, which are described in Table 8.
Table 8. Frequency and Phase Registers
Register Size Description
FREQ0
28 bits
Frequency Register 0.
When the FSEL bit or FSELECT pin = 0, the
FREQ0 register defines the output frequency
as a fraction of the MCLK frequency.
FREQ1
28 bits
Frequency Register 1.
When the FSEL bit or FSELECT pin = 1, the
FREQ1 register defines the output frequency
as a fraction of the MCLK frequency.
PHASE0
12 bits
Phase Offset Register 0.
When the PSEL bit or PSELECT pin = 0, the
contents of the PHASE0 register are added
to the output of the phase accumulator.
PHASE1
12 bits
Phase Offset Register 1.
When the PSEL bit or PSELECT pin = 1, the
contents of the PHASE1 register are added
to the output of the phase accumulator.
The analog output from the AD9838 is
fMCLK/228 × FREQREG
where FREQREG is the value loaded into the selected frequency
register.
This signal is phase shifted by
2π/4096 × PHASEREG
where PHASEREG is the value contained in the selected phase
register.
The relationship of the selected output frequency and the refer-
ence clock frequency must be considered to avoid unwanted
output anomalies.
Selecting a Frequency or Phase Register
Access to the frequency and phase registers is controlled by
the FSELECT and PSELECT pins or by the FSEL and PSEL
control bits. If the PIN/SW control bit (Bit D9) = 1, the pins
control the function; if the PIN/SW control bit = 0, the bits
control the function (see Table 9 and Table 10). If the FSEL
and PSEL bits are used, the pins should be held at CMOS logic
high or low. Control of the frequency and phase registers is
interchangeable from the pins to the bits.
Table 9. Selecting a Frequency Register
FSELECT Pin FSEL Bit PIN/SW Bit
0
X
1
1
X
1
X
0
0
X
1
0
Selected Register
FREQ0
FREQ1
FREQ0
FREQ1
AD9838
Table 10. Selecting a Phase Register
PSELECT Pin PSEL Bit PIN/SW Bit
0
X
1
1
X
1
X
0
0
X
1
0
Selected Register
PHASE0
PHASE1
PHASE0
PHASE1
The FSELECT and PSELECT pins are sampled on the internal
falling edge of MCLK. It is recommended that the data on these
pins not change within the time window of the falling edge of
MCLK (see Figure 3 for timing). If the FSELECT or PSELECT
pin changes value when a falling edge occurs, there is an uncer-
tainty of one MCLK cycle as it pertains to when control is
transferred to the other frequency/phase register.
The flowcharts in Figure 26 and Figure 27 show the routine for
selecting and writing to the frequency and phase registers of the
AD9838.
Writing to a Frequency Register
When writing to a frequency register, Bit D15 and Bit D14 of
the control register give the address of the frequency register
(see Table 11).
Table 11. Frequency Register Bits
D15
D14
D13 to D0
0
1
14 FREQ0 register bits
1
0
14 FREQ1 register bits
To change the entire contents of a frequency register, two consec-
utive writes to the same address must be performed because the
frequency registers are 28 bits wide. The first write contains the
14 LSBs, and the second write contains the 14 MSBs. For this
mode of operation, the B28 control bit (Bit D13) must be set
to 1. An example of a 28-bit write is shown in Table 12.
Table 12. Writing 0xFFFC000 to the FREQ0 Register
SDATA Input
Result of Input Word
0010 0000 0000 0000
Control word write
(D15, D14 = 00), B28 (D13) = 1,
HLB (D12) = X
0100 0000 0000 0000
FREQ0 register write
(D15, D14 = 01), 14 LSBs = 0x0000
0111 1111 1111 1111
FREQ0 register write
(D15, D14 = 01), 14 MSBs = 0x3FFF
Note, however, that continuous writes to the same frequency
register may result in intermediate updates during the writes. If
a frequency sweep, or something similar, is required, it is recom-
mended that users alternate between the two frequency registers.
Rev. A | Page 19 of 32
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