AD9848 查看數據表（PDF） - Analog Devices
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AD9848 Datasheet PDF : 36 Pages
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AD9848/AD9849
H-Driver and RG Outputs
In addition to the programmable timing positions, the AD9848/
AD9849 features on-chip output drivers for the RG and H1–H4
outputs. These drivers are powerful enough to directly drive the
CCD inputs. The H-driver current can be adjusted for optimum
rise/fall time into a particular load by using the DRV registers. The
RG drive current is adjustable using the RGDRV register. Each
3-bit DRV register is adjustable in 3.5 mA increments, with the
minimum setting of 0 equal to OFF or three-state, and the maxi-
mum setting of 7 equal to 24.5 mA.
As shown in Figure 7, the H2/H4 outputs are inverses of H1/
H3. The internal propagation delay resulting from the signal
inversion is less than l ns, which is significantly less than the
typical rise time driving the CCD load. This results in a H1/H2
crossover voltage at approximately 50% of the output swing.
The crossover voltage is not programmable.
Digital Data Outputs
The AD9848/AD9849 data output phase is programmable
using the DOUTPHASE register. Any edge from 0 to 47 may
be programmed, as shown in Figure 8.
Register Name
POL
POSLOC
NEGLOC
DRV
Length
1b
6b
6b
3b
Table II. H1–H4, RG, SHP, SHD Timing Parameters
Range
Description
High/Low
0–47 Edge Location
0–47 Edge Location
0–7 Current Steps
Polarity Control for H1, H3, and RG (0 = No Inversion, 1 = Inversion)
Positive Edge Location for H1, H3, and RG
Sample Location for SHP, SHD
Negative Edge Location for H1, H3, and RG
Drive Current for H1–H4 and RG Outputs (3.5 mA Per Step)
Quadrant
I
II
III
IV
Table III. Precision Timing Edge Locations
Edge Location (Decimal)
0 to 11
12 to 23
24 to 35
36 to 47
Register Value (Decimal)
0 to 11
16 to 27
32 to 43
48 to 59
Register Value (Binary)
000000 to 001011
010000 to 011011
100000 to 101011
110000 to 111011
POSITION
PIXEL
PERIOD
RG
H1/H3
P[0]
RGr[0]
Hr[0]
P[12]
RGf[12]
CCD SIGNAL
P[24]
P[36]
P[48] = P[0]
Hf[24]
SHP[28]
SHD[48]
tS1
NOTES
1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 48 POSITIONS WITHIN ONE PIXEL PERIOD.
2. DEFAULT POSITIONS FOR EACH SIGNAL ARE SHOWN ABOVE.
Figure 6. High-Speed Clock Default and Programmable Locations
–20–
REV. 0
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