AD9861 查看數據表（PDF） - Analog Devices
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AD9861 Datasheet PDF : 52 Pages
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AD9861
TIMING SPECIFICATIONS
Table 5. AD9861-50 and AD9861-80
Parameter
INPUT CLOCK
CLKIN Clock Rate (PLL Bypassed)
PLL Input Frequency
PLL Ouput Frequency
TxPATH DATA
Setup Time (HD20 Mode, Time Required Before Data Latching
Edge)
Temp
Full
Full
Full
Full
Test Level
IV
IV
IV
V
Hold Time (HD20 Mode, Time Required After Data Latching
Full
V
Edge)
Latency 1× Interpolation (data in until peak output response) Full
V
Latency 2× Interpolation (data in until peak output response) Full
V
Latency 4× Interpolation (data in until peak output response) Full
V
RxPATH DATA
Output Delay (HD20 Mode, tOD)
Full
V
Latency
Full
V
Min Typ Max Unit
1
200 MHz
16
200 MHz
32
350 MHz
5
ns (see Clock
Distribution Block
section)
–1.5
ns (see Clock
Distribution Block
section)
7
DAC Clock Cycles
35
DAC Clock Cycles
83
DAC Clock Cycles
–1.5
ns (see Clock
Distribution Block
section)
5
ADC Clock Cycles
Table 6. Explanation of Test Levels
Level Description
I
100% production tested.
II
100% production tested at 25°C and guaranteed by design and characterization at specified temperatures.
III
Sample tested only.
IV
Parameter is guaranteed by design and characterization testing.
V
Parameter is a typical value only.
VI
100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range.
Rev. 0 | Page 6 of 52
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