AD9866 查看數據表（PDF） - Analog Devices
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AD9866 Datasheet PDF : 48 Pages
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AD9866
FULL-DUPLEX DATA INTERFACE (Tx AND Rx PORT) TIMING SPECIFICATIONS
Table 7. AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted
Parameter
Temp
Test Level
Min
Typ
Max
Tx PATH INTERFACE (See Figure 53)
Input Nibble Rate (2× Interpolation)
Full
II
20
160
Input Nibble Rate (4× Interpolation)
Full
II
10
100
Tx Data Setup Time (tDS)
Full
II
3
Tx Data Hold Time (tDH)
Full
II
1
Rx PATH INTERFACE (See Figure 54)
Output Nibble Rate
Full
II
10
160
Rx Data Valid Time (tDV)
Full
II
3
Rx Data Hold Time (tDH)
Full
II
0
Explanation of Test Levels
I: 100% production tested.
II: 100% production tested at 25°C and guaranteed by design and characterization at specified temperatures.
III: Sample tested only.
IV: Parameter is guaranteed by design and characterization testing.
V: Parameter is a typical value only.
VI: 100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range.
Unit
MSPS
MSPS
ns
ns
MSPS
ns
ns
Rev. 0 | Page 8 of 48
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