AD9874 查看數據表（PDF） - Analog Devices

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AD9874

IF Digitizing Subsystem

Analog Devices 

AD9874

(VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = VDDx, VDDQ = VDDP = 5.0 V, fCLK = 18 MSPS, fIF = 109.56 MHz, fLO = 107.4 MHz,

TA = 25؇C, LO = –5 dBm, LO and CLK Synthesizer Disabled, 16-Bit Data with AGC and DVGA enabled, unless otherwise noted.)1

0.1

9.0

0

–12

HIGH BIAS

0

8.8

–10

–15

–0.1

LOW BIAS

–0.2

HIGH BIAS

–0.3

–0.4

–0.5

–0.6

–0.7

8.6

NF-HIGH BIAS

–20

–18

8.4

8.2

–30

–21

NF-LOW BIAS

8.0

–40

–24

7.8

–50

–27

IMD-LOW BIAS

7.6

–60

–30

7.4

7.2

IMD-HIGH BIAS

–70

–33

LOW BIAS

–0.8

–20 –17 –14 –11

–8

–5

LO DRIVE – dBm

7.0

–20

–15 –10

–5

0

LO DRIVE – dBm

–80

5

–36

–36 –30 –24 –18 –12 –6

0

IFIN – dBm

TPC 7a. Normalized Gain Variation

vs. LO Drive (VDDx = 3.0 V)

TPC 7b. Noise Figure and IMD

vs. LO Drive (VDDx = 3.0 V)

TPC 7c. Gain Compression vs. IFIN

with 16 dB LNA Attenuator Enabled

0

–2.8dBFS OUTPUT

–20

–40

NBW = 3.66kHz

fCLK = 18MHz

MAX VGA ATTEN

DEC–BY–120

–60

–80

–100

–120

–140

–80 –60 –40 –20 0 20 40 60 80

FREQUENCY – kHz

TPC 8a. Complex FFT of Baseband

I/Q for Single-Tone (High Bias)

0

–18.2dBFS OUTPUT

–20

–40

NBW = 3.66kHz

fCLK = 18MHz

MAX VGA ATTEN

DEC–BY–120

–60

–80

–100

IMD = 74dBc

–120

–140

–80 –60 –40 –20 0 20 40 60 80

FREQUENCY – kHz

TPC 9a. Complex FFT of Baseband

I/Q for Dual Tone IMD (High Bias

with Each IFIN Tone @ –35 dBm)

0

ADC GOES INTO

HARD COMPRESSION

–2

3.6V

3.3V

–4

–6

3.0V

–8

2.7V

–10

–12

–14

–30 –28 –26 –24 –22 –20 –18 –16

IFIN – dBm

TPC 8b. Gain Compression vs. IFIN

(High Bias2)

0

ADC DOES NOT GO INTO

HARD COMPRESSION

–2

3.6V

3.3V

–4

–6

3.0V

–8

2.7V

–10

–12

–14

–30 –28 –26 –24 –22 –20 –18 –16 –14

IFIN – dBm

TPC 8c. Gain Compression vs. IFIN

(Low Bias3)

–70

–15

–76

–18

PIN

–82

–21

2.7V

–88

–24

–94

–100

–106

–112

–118

–27

3.0V

–30

3.3V

–33

–36

3.6V

–39

–124

–42

–130

–45

–51 –48 –45 –42 –39 –36 –33 –30

IFIN – dBm

TPC 9b. IMD vs. IFIN (High Bias2)

–55

–15

–61

–18

PIN

–67

–21

2.7V

–73

–24

–79

–27

3.0V

–85

–30

3.3V

–91

–33

–97

–103

–36

3.6V

–39

–109

–42

–115

–45

–51 –48 –45 –42 –39 –36 –33 –30

IFIN – dBm

TPC 9c. IMD vs. IFIN (Low Bias3)

1Data taken with Toko FSLM series 10 µH inductors.

2High Bias corresponds to LNA_Mixer Setting of 33 in SPI Register 0x01.

3Low Bias corresponds to LNA_Mixer Setting of 12 in SPI Register 0x01.

–10–

REV. A

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