AD9874 查看數據表（PDF） - Analog Devices
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AD9874 Datasheet PDF : 40 Pages
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AD9874–Typical Performance Characteristics
(VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = VDDx, VDDQ = VDDP = 5.0 V, fCLK = 18 MSPS, fIF = 109.56 MHz, fLO = 107.4 MHz,
TA = 25؇C, LO = –5 dBm, LO and CLK Synthesizer Disabled, 16-Bit Data with AGC and DVGA enabled, unless otherwise noted.)1
9.5
9.5
100
80
–40؇C
60
+25؇C
+85؇C
40
20
0
7.2 7.5 7.8 8.1 8.4 8.7 9.0
NOISE FIGURE – dB
9.0
+85؇C
8.5
+25؇C
8.0
7.5
–40؇C
7.0
6.5
6.0
2.7
3.0
3.3
3.6
VDDx – V
9.0
+85؇C
8.5
8.0
+25؇C
7.5
7.0
–40؇C
6.5
6.0
2.7
3.0
3.3
3.6
VDDx – V
TPC 1a. CDF of SSB Noise Figure
(VDDx = 3.0 V, High Bias2)
TPC 1b. SSB Noise Figure vs. Supply
(High Bias2)
TPC 1c. SSB Noise Figure vs. Supply
(Low Bias3)
100
80
–40؇C
60
+25؇C +85؇C
40
20
0
–3
–2
–1
0
1
2
IIP3 – dBm
TPC 2a. CDF of IIP3 (VDDx = 3.0 V,
High Bias2)
1.5
1.0
+85؇C
0.5
0
–0.5
–1.0
+25؇C
–1.5
–40؇C
–2.0
–2.5
–3.0
–3.5
2.7
3.0
3.3
3.6
VDDx – V
TPC 2b. IIP3 vs. Supply (High Bias2)
0
–2
–4
+85؇C
–6
+25؇C
–8
–40؇C
–10
–12
2.7
3.0
3.3
3.6
VDDx – V
TPC 2c. IIP3 vs. Supply (Low Bias3)
100
80
–40؇C
60
40
20
+85؇C
+25؇C
0
92 93 94 95 96 97 98
DYNAMIC RANGE – dB
TPC 3a. CDF of Dynamic Range
(VDDx = 3.0 V, High Bias2)
98
97
–40؇C
96
95
+85؇C
94
+25؇C
93
92
2.7
3.0
3.3
3.6
VDDx – V
TPC 3b. Dynamic Range vs. Supply
(High Bias2)
98
97
+25؇C
96
95
–40؇C
94
+85؇C
93
92
2.7
3.0
3.3
3.6
VDDx – V
TPC 3c. Dynamic Range vs. Supply
(Low Bias3)
1Data taken with Toko FSLM series 10 µH inductors.
2High Bias corresponds to LNA_Mixer Setting of 33 in SPI Register 0x01.
3Low Bias corresponds to LNA_Mixer Setting of 12 in SPI Register 0x01.
–8–
REV. A
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