AD9878 查看數據表（PDF） - Analog Devices
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AD9878 Datasheet PDF : 36 Pages
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AD9878
PARAMETER
TIMING CHARACTERISTICS (10 pF Load)
Wake-Up Time
Minimum RESET Pulse Width Low, tRL
Digital Output Rise/Fall Time
Tx/Rx Interface
MCLK Frequency, fMCLK
TxSYNC/TxIQ Setup Time, tSU
TxSYNC/TxIQ Hold Time, tHU
MCLK Rising Edge to RxSYNC Valid Delay, tMD
REFCLK Rising or Falling Edge to
RxSYNC Valid Delay, tOD
REFCLK Edge to MCLK Falling Edge, tEE
SERIAL CONTROL BUS
Maximum SCLK Frequency, fSCLK
Minimum Clock Pulse Width High, tPWH
Minimum Clock Pulse Width Low, tPWL
Maximum Clock Rise/Fall Time
Minimum Data/Chip-Select Setup Time, tDS
Minimum Data Hold Time, tDH
Maximum Data Valid Time, tDV
CMOS LOGIC INPUTS
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Input Capacitance
CMOS LOGIC OUTPUTS (1 mA Load)
Logic 1 Voltage
Logic 0 Voltage
POWER SUPPLY
Supply Current, IS (Full Operation)
Analog Supply Current, IAS
Digital Supply Current, IDS
Supply Current, IS
Standby (PWRDN Pin Active, IAS + IDS )
Full Power-Down (Register 0x02 = 0xFF)
Power-Down Tx Path (Register 0x02 = 0x60)
Power-Down IF12 Rx Path (Register 0x02 = 0x1B)
Power Supply Rejection (Differential Signal)
Tx DAC
10-Bit ADC
12-Bit ADC
Temp
N/A
N/A
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Test Level Min
Typ
N/A
N/A
5
II
2.8
II
II
3
II
3
II
0
II
tOSCIN/
4 − 2.0
II
−1.0
II
II
30
II
30
II
II
25
II
0
II
II
VDRVDD − 0.7
II
II
II
III
3
II
VDRVDD − 0.6
II
II
184
III
105
III
79
II
124
II
46
III
124
III
131
III
<0.25
III
<0.0001
III
<0.0004
Max
200
4
58
1.0
tOSCIN/
4 + 3.0
+1.0
15
1
30
0.4
12
12
0.4
204
115
89
137
52
159
Unit
tMCLK cycles
tMCLK cycles
ns
MHz
ns
ns
ns
ns
ns
MHz
ns
ns
µs
ns
ns
ns
V
V
µA
µA
pF
V
V
mA
mA
mA
mA
mA
mA
mA
% FS
% FS
% FS
Rev. A | Page 6 of 36
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