AD9878 查看數據表（PDF） - Analog Devices
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AD9878 Datasheet PDF : 36 Pages
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AD9878
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
DRGND 1
DRVDD 2
(MSB) IF12(11) 3
IF12(10) 4
IF12(9) 5
IF12(8) 6
IF12(7) 7
IF12(6) 8
IF12(5) 9
IF12(4) 10
IF12(3) 11
IF12(2) 12
IF12(1) 13
IF12(0) 14
(MSB) IF10(4) 15
IF10(3) 16
IF10(2) 17
IF10(1) 18
IF10(0) 19
RxSYNC 20
DRGND 21
DRVDD 22
MCLK 23
DVDD 24
DGND 25
AD9878
TOP VIEW
(Not to Scale)
75 REFT10
74 REFB10
73 AGND10
72 AVDD10
71 DRVDD
70 DRGND
69 REFCLK
68 SIGDELT
67 FLAG1
66 FLAG2
65 CA_EN
64 CA_DATA
63 CA_CLK
62 DVDDOSC
61 OSCIN
60 XTAL
59 DGNDOSC
58 AGNDPLL
57 PLLFILT
56 AVDDPLL
55 DVDDPLL
54 DGNDPLL
53 AVDDTx
52 Tx+
51 Tx–
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
1, 21, 70
DRGND
2, 22, 71
DRVDD
3
(MSB) IF12(11)
4 to 14
IF12[10:0]
15
(MSB) IF10(4)
16 to 19
IF10[3:0]
20
RxSYNC
23
MCLK
24, 33, 35, 39
DVDD
25, 34, 36, 40
DGND
26
TxSYNC
27
(MSB) TxIQ(5)
28 to 32
TxIQ[4:0]
37
PROFILE
38
RESET
41
SCLK
42
CS
43
SDIO
Descriptions
Pin Driver Digital Ground
Pin Driver Digital 3.3 V Supply
12-Bit ADC Digital Ouput
12-Bit ADC Digital Ouput
10-Bit ADC Digital Ouput
10-Bit ADC Digital Ouput
Sync Output, 10-Bit and 12-Bit ADCs
Master Clock Output
Digital 3.3 V Supply
Digital Ground
Sync Input for Transmit Port
Digital Input for Transmit Port
Digital Input for Transmit Port
Profile Selection Input
Chip Reset Input
SPORT Clock
SPORT Chip Select
SPORT Data I/O
Rev. A | Page 8 of 36
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