AD9923A 查看數據表（PDF） - Analog Devices

零件编号

产品描述 (功能)

生产厂家

AD9923A

CCD Signal Processor with V-Driver and Precision Timing Generator

Analog Devices 

AD9923A

Table 11. Precision Timing Edge Locations

Quadrant

Edge Location (Decimal)

I

0 to 11

II

12 to 23

III

24 to 35

IV

36 to 47

Register Value (Decimal)

0 to 11

16 to 27

32 to 43

48 to 59

Register Value (Binary)

000000 to 001011

010000 to 011011

100000 to 101011

110000 to 111011

POSITION

P[0]

CLI

tCLIDLY

1 PIXEL

PERIOD

P[12]

P[24]

P[36]

P[48] = P[0]

NOTES

1. THE PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCK.

2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITION (tCLIDLY = 6ns TYP).

Figure 17. High Speed Clock Resolution from CLI Master Clock Input

CCD

SIGNAL

1

2

RG

5

HL

7

H1

H2

9

H3

3

4

6

8

10

H4

PROGRAMMABLE CLOCK POSITIONS:

1RG RISING EDGE.

2RG FALLING EDGE.

3SHP SAMPLE LOCATION.

4SHD SAMPLE LOCATION.

5HL RISING EDGE POSITION.

6HL FALLING EDGE POSITION.

7H1 RISING EDGE POSITION.

8H1 FALLING EDGE POSITION (H2 IS INVERSE OF H1).

9H3 RISING EDGE POSITION.

10H3 FALLING EDGE POSITION (H4 IS INVERSE OF H3).

Figure 18. High Speed Clock Programmable Locations

Rev. A | Page 16 of 84

Share Link: