AD9923A 查看數據表（PDF） - Analog Devices

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AD9923A

CCD Signal Processor with V-Driver and Precision Timing Generator

Analog Devices 

AD9923A

Individual HBLK Patterns

The HBLK programmable timing shown in Figure 26 is similar

to CLPOB and PBLK; however, there is no start polarity control.

Only the toggle positions are used to designate the start and end

positions of the blanking period. Additionally, there is a polarity

control register, HBLKMASK, that designates the polarity of the

horizontal clock signals during the blanking period. Setting

HBLKMASK high sets H1 = H3 = high and H2 = H4 = low

during blanking, as shown in Figure 27. As with CLPOB and

PBLK registers, HBLK registers are available in each V-sequence,

allowing different blanking signals to be used with different

vertical timing sequences.

Note that 8189 is the recommended setting for any unused

HBLK toggle locations on the AD9923A, regardless of the

setting for HBLKALT. 8190 and 8191 are not valid settings for

HBLK toggle positions that are unused and causes undesired

HBLK toggle activity.

Generating Special HBLK Patterns

There are six toggle positions available for HBLK. Normally,

only two of the toggle positions are used to generate the

standard HBLK interval. However, additional toggle positions

can be used to generate special HBLK patterns, as shown in

Figure 28. The pattern in this example uses all six toggle

positions to generate two extra groups of pulses during the

HBLK interval. By changing the toggle positions, different

patterns can be created.

Table 13. HBLK Pattern Registers

Register

Length

(Bits) Range

HBLKMASK 1

High/low

HBLKALT

3

0 to 7 alternation modes

HBLKTOGE1 13

HBLKTOGE2 13

HBLKTOGE3 13

HBLKTOGE4 13

HBLKTOGE5 13

HBLKTOGE6 13

HBLKLEN 13

HBLKREP

8

HBLKTOGO1 13

HBLKTOGO2 13

HBLKTOGO3 13

HBLKTOGO4 13

HBLKTOGO5 13

HBLKTOGO6 13

0 to 8189 pixel location

0 to 8189 pixel location

0 to 8189 pixel location

0 to 8189 pixel location

0 to 8189 pixel location

0 to 8189 pixel location

0 to 8189 pixels

0 to 255 repetitions

0 to 8189 pixel location

0 to 8189 pixel location

0 to 8189 pixel location

0 to 8189 pixel location

0 to 8189 pixel location

0 to 8189 pixel location

Description

Masking polarity for H1, H3, HL (0 = mask low, 1 = mask high)

Enables different odd/even alternation of HBLK toggle positions

0: disable alternation (HBLKTOGE1 to HBLKTOGE6 registers are used for each line)

1: TOGE1 and TOGE2 odd lines, TOGE3 to TOGE6 even lines

2: TOGE1 and TOGE2 even lines, TOGE3 to TOGE6 odd lines

3: TOGE1 to TOGE6 even lines, TOGO1 to TOGE6 odd lines (FREEZE/RESUME not

available)

4 to 7: HBLKSTART, HBLKEND, HBLKLEN, and HBLKREP registers are used for each line

HBLK first toggle position (for even lines only when HBLKALT = 3)

HBLK second toggle position (for even lines only when HBLKALT = 3)

HBLK third toggle position (for even lines only when HBLKALT = 3)

HBLK fourth toggle position (for even lines only when HBLKALT = 3)

Fifth toggle position, even lines (HBLKSTART when HBLKALT = 4 to 7)

Sixth toggle position, even lines (HBLKEND when HBLKALT = 4 to 7)

HBLK pattern length, only used when HBLKALT = 4 to 7

Number of HBLK pattern repetitions, only used when HBLKALT = 4 to 7

First toggle position for odd lines when HBLKALT = 3 (usually VREPA_3)

Second toggle position for odd lines when HBLKALT = 3 (usually VREPA_4)

Third toggle position for odd lines when HBLKALT = 3 (usually FREEZE1)

Fourth toggle position for odd lines when HBLKALT = 3 (usually RESUME1)

Fifth toggle position for odd lines when HBLKALT = 3 (usually FREEZE2)

Sixth toggle position for odd lines when HBLKALT = 3 (usually RESUME2)

HD

HBLK

HBLKTOGE1

HBLKTOGE2

BLANK

BLANK

BASIC HBLK PULSE IS GENERATED USING HBLKTOGE1 AND HBLKTOGE2 REGISTERS (HBLKALT = 0).

Figure 26. Typical Horizontal Blanking (HBLK) Pulse Placement

Rev. A | Page 20 of 84

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