AD-DPGIOZ 查看數據表（PDF） - Analog Devices
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AD-DPGIOZ Datasheet PDF : 61 Pages
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Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AD9961/AD9963
AUX33V 1
AUXADCREF 2
RXQP 3
RXQN 4
RXGND 5
RXBIAS 6
RX18V 7
RX33V 8
RX18VF 9
RXCML 10
RXGND 11
RXIN 12
RXIP 13
LDO_EN 14
RESET 15
SCLK 16
CS 17
SDIO 18
PIN 1
INDICATOR
AD9961
(TOP VIEW)
54 DLLFILT
53 DLL18V
52 DVDD18
51 DRVDD
50 NC
49 NC
48 TXD0
47 TXD1
46 TXD2
45 TXD3
44 TXD4
43 TXD5
42 TXD6
41 TXD7
40 TXD8
39 TXD9
38 TXIQ/TXnRX
37 TXCLK
NOTES
1. EXPOSED PAD MUST BE SOLDERED TO PCB.
2. NC = NO CONNECT.
Figure 2. AD9961 Pin Configuration
Table 8. AD9961 Pin Function Descriptions
Pin No. Mnemonic
Description
1
AUX33V
Analog Supply for the Auxiliary ADC and Auxiliary DACs (3.3 V ± 5%, 1.8 V ± 5% If Auxiliary ADC Is
Powered Down).
2
AUXADCREF
Reference Output (Or Input) for Auxiliary ADC.
3, 4
RXQP, RXQN
Differential ADC Q Inputs. The default full-scale input voltage range is 1.56 V p-p differential.
5, 11
RXGND
Receive Path Ground.
6
RXBIAS
External Bias Resistor Connection. An optional 10 kΩ resistor can be connected between this pin and the
analog ground to improve the accuracy of the full-scale range of the Rx ADCs.
7
RX18V
Output of RX18V Voltage Regulator.
8
RX33V
Input to RX18V and RX18VF Voltage Regulators (2.5 V to 3.3 V). If LDOs are not being used, short Pin 8 to
Pin 7.
9
RX18VF
Output of RX18VF Voltage Regulator.
10
RXCML
ADC Common-Mode Voltage Output.
12, 13
RXIN, RXIP
Differential ADC I Inputs. The default full-scale input voltage range is 1.56 V p-p differential.
14
LDO_EN
Control Pin for LDOs (GND = Disable all LDOs, Float = Enable DVDD18 LDO Only, DRVDD = Enable All
LDOs).
15
RESET
Reset. Active low to reset the configuration registers to default values and reset device.
16
SCLK
Clock Input for Serial Port.
17
CS
Active Low Chip Select.
18
SDIO
Bidirectional Data Line for Serial Port.
19, 34
DGND
Digital Core Ground.
20, 33, 51 DRVDD
Input/Output Pad Ring Supply Voltage (1.8 V to 3.3 V).
21 to 30 TRXD9 to TRXD0 ADC Output Data in Full Duplex Mode. ADC output data and DAC input data in half-duplex mode.
31, 32,
NC
49, 50
Not Connected.
35
TRXIQ
Output Signal Indicating from Which ADC the Output Data Is Sourced.
Rev. A | Page 9 of 60
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