AD9981 查看數據表（PDF） - Analog Devices
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AD9981 Datasheet PDF : 44 Pages
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AD9981
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
VD (3.3V) 1
BAIN0 2
GND 3
BAIN1 4
VD (3.3V) 5
GAIN0 6
GND 7
SOGIN0 8
VD (3.3V) 9
GAIN1 10
GND 11
SOGIN1 12
VD (3.3V) 13
RAIN0 14
GND 15
RAIN1 16
PWRDN 17
REFLO 18
REFCM 19
REFHI 20
PIN 1
AD9981
TOP VIEW
(Not to Scale)
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
60 BLUE <3>
59 BLUE <4>
58 BLUE <5>
57 BLUE <6>
56 BLUE <7>
55 BLUE <8>
54 BLUE <9>
53 GND
52 VDD (3.3V)
51 GREEN <0>
50 GREEN <1>
49 GREEN <2>
48 GREEN <3>
47 GREEN <4>
46 GREEN <5>
45 GREEN <6>
44 GREEN <7>
43 GREEN <8>
42 GREEN <9>
41 DAVDD (1.8)
Figure 2. Top View (Pins Down)
Table 3. Complete Pinout List
Pin Type
Mnemonic
Inputs
RAIN0
RAIN1
GAIN0
GAIN1
BAIN0
BAIN1
HSYNC0
HSYNC1
VSYNC0
VSYNC1
SOGIN0
SOGIN1
EXTCK
CLAMP
COAST
PWRDN
Outputs
RED [9:0]
GREEN [9:0]
BLUE [9:0]
DATACK
Function
Channel 0 Analog Input for Converter R
Channel 1 Analog Input for Converter R
Channel 0 Analog Input for Converter G
Channel 1 Analog Input for Converter G
Channel 0 Analog Input for Converter B
Channel 1 Analog Input for Converter B
Horizontal Sync Input for Channel 0
Horizontal Sync Input for Channel 1
Vertical Sync Input for Channel 0
Vertical Sync Input for Channel 1
Input for Sync-on-Green Channel 0
Input for Sync-on-Green Channel 1
External Clock Input
External Clamp Input Signal
External PLL Coast Signal Input
Power-Down Control
Outputs of Converter R, Bit 9 is the MSB
Outputs of Converter G, Bit 9 is the MSB
Outputs of Converter B, Bit 9 is the MSB
Data Output Clock
Rev. 0 | Page 6 of 44
Value
0.0 V to 1.0 V
0.0 V to 1.0 V
0.0 V to 1.0 V
0.0 V to 1.0 V
0.0 V to 1.0 V
0.0 V to 1.0 V
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
0.0 V to 1.0 V
0.0 V to 1.0 V
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
Pin No.
14
16
6
10
2
4
70
68
71
69
8
12
721
73
721
17
28 to 37
42 to 51
54 to 63
25
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