MAX145AMJA(1998) 查看數據表（PDF） - Maxim Integrated
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MAX145AMJA
(Rev.:1998)
(Rev.:1998)
Maxim Integrated
MAX145AMJA Datasheet PDF : 16 Pages
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+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin µMAX
TIMING CHARACTERISTICS (Figure 7)
(VDD = +2.7V to +5.25V, VREF = 2.5V, 0.1µF capacitor at REF, fSCLK = 2.17MHz, 16 clocks/conversion cycle (108ksps),
CH- = GND for MAX145, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Wake-Up Time (Note 10)
tWAKE
2.5
CS/SHDN Fall to Output Enable
tDV
CL = 100pF
CS/SHDN Rise to Output Disable
tTR
CL = 100pF, Figure 1
SCLK Fall to Output Data Valid
tDO CL = 100pF, Figure 1
20
SCLK Clock Frequency
External clock
0.1
fSCLK Internal clock, SCLK for data transfer only
0
µs
120
ns
120
ns
120
ns
2.17
MHz
5
External clock
215
SCLK Pulse Width High
tCH
Internal clock, SCLK for data transfer only
(Note 8)
50
ns
External clock
215
SCLK Pulse Width Low
tCL
Internal clock, SCLK for data transfer only
(Note 8)
50
ns
ns
SCLK to CS/SHDN Setup
CS/SHDN Pulse Width
tSCLKS
tCS
60
ns
60
ns
Note 1: Tested at VDD = +2.7V.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after full-scale range has been
calibrated.
Note 3: Offset nulled.
Note 4: “On” channel is grounded; sine wave applied to “off” channel (MAX144 only).
Note 5: Conversion time is defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 6: The common-mode range for the analog inputs is from GND to VDD (MAX145 only).
Note 7: ADC performance is limited by the converter’s noise floor, typically 300µVp-p.
Note 8: Guaranteed by design. Not subject to production testing.
Note 9: Measured as VFS(2.7V) - VFS(5.25V).
Note 10: SCLK must remain stable during this time.
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