ADC0808S125 查看數據表（PDF） - Integrated Device Technology

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ADC0808S125

Single 8-bit ADC, up to 125 MHz or 250 MHz

Integrated Device Technology 

Integrated Device Technology

ADC0808S125/250

Single 8-bit ADC, up to 125 MHz or 250 MHz

Table 4. Clock input format selection

Pin CLKSEL

HIGH or not connected

LOW

Clock input signal

Pins CLK+ and CLK

LVDS

1.8 V CMOS

7.2 Digital output coding

The digital outputs are 1.8 V CMOS compatible.

The data output format can be either binary or 2’s complement.

Table 5. Output coding with differential inputs

Vi(p-p) = 2.0 V; Vref(fs) = 1.25 V; typical values to AGND.

Code

Inputs (V)

Output

Underflow

Vi(IN)

< 0.45

Vi(INN)

> 1.45

Pin IR

LOW

0

0.45

1.45

HIGH

1

-

-

HIGH

:

:

:

:

127

0.95

0.95

HIGH

:

:

:

:

254

-

-

HIGH

255

1.45

0.45

HIGH

Overflow > 1.45

< 0.45

LOW

Outputs D7 to D0

Binary

2’s complement

0000 0000

1000 0000

0000 0000

1000 0000

0000 0001

1000 0001

:

:

0111 1111

1111 1111

:

:

1111 1110

0111 1110

1111 1111

0111 1111

1111 1111

0111 1111

The in-range CMOS output pin IR will be HIGH during normal operation. When the ADC

input reaches either positive or negative full-scale, the IR output will be LOW.

Selection between output coding is controlled by pins OTC and CE_N.

Table 6. Output format selection

2’s complement outputs Chip enable

Pin OTC

Pin CE_N

LOW

LOW

HIGH

LOW

X [1]

HIGH

Output data

Pins D0 to D7, CCS and IR

active; binary

active; 2’s complement

high-impedance

[1] X = don’t care.

ADC0808S125_ADC0808S250_4

Product data sheet

Rev. 04 — 2 July 2012

© IDT 2012. All rights reserved.

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