ADM1066ASU-REEL 查看數據表（PDF） - Analog Devices

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ADM1066ASU-REEL

Super Sequencer™ with Margining Control and Auxiliary ADC Inputs

Analog Devices 

ADM1066

Parameter

DIGITAL INPUTS (VXn, A0, A1)

Input High Voltage, VIH

Input Low Voltage, VIL

Input High Current, IIH

Input Low Current, IIL

Input Capacitance

Programmable Pull-Down Current,

IPULL-DOWN

SERIAL BUS DIGITAL INPUTS (SDA, SCL)

Input High Voltage, VIH

Input Low Voltage, VIL

Output Low Voltage, VOL 2

SERIAL BUS TIMING

Clock Frequency, fSCLK

Bus Free Time, tBUF

Start Setup Time, tSU;STA

Start Hold Time, tHD;STA

SCL Low Time, tLOW

SCL High Time, tHIGH

SCL, SDA Rise Time, tr

SCL, SDA Fall Time, tf

Data Setup Time, tSU;DAT

Data Hold Time, tHD;DAT

Input Low Current, IIL

SEQUENCING ENGINE TIMING

State Change Time

Min

Typ Max Unit Test Conditions/Comments

2.0

V

Maximum VIN = 5.5 V

0.8

V

Maximum VIN = 5.5 V

−1

µA

VIN = 5.5 V

1

µA

VIN = 0

5

pF

20

µA

VDDCAP = 4.75, TA = 25°C, if known logic state is

required

2.0

V

0.8

V

0.4

V

IOUT = −3.0 mA

400 kHz

4.7

µs

4.7

µs

4

µs

4.7

µs

4

µs

1000 µs

300 µs

250

ns

5

ns

1

µA

VIN = 0

10

µs

1 At least one of the VH, VP1-4 pins must be ≥3.0 V to maintain the device supply on VDDCAP.

2 Specification is not production tested, but is supported by characterization data at initial product release.

Rev. 0 | Page 6 of 32

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