ADM1066ASU-REEL 查看數據表（PDF） - Analog Devices
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ADM1066ASU-REEL Datasheet PDF : 32 Pages
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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADM1066
40 39 38 37 36 35 34 33 32 31
VX1 1
VX2 2
VX3 3
VX4 4
VX5 5
VP1 6
VP2 7
VP3 8
VP4 9
VH 10
PIN 1
INDICATOR
ADM1066
TOP VIEW
(Not to Scale)
30 PDO1
29 PDO2
28 PDO3
27 PDO4
26 PDO5
25 PDO6
24 PDO7
23 PDO8
22 PDO9
21 PDO10
11 12 13 14 15 16 17 18 19 20
48 47 46 45 44 43 42 41 40 39 38 37
NC 1
VX1 2
VX2 3
VX3 4
VX4 5
VX5 6
VP1 7
VP2 8
VP3 9
VP4 10
VH 11
NC 12
PIN 1
INDICATOR
ADM1066
TOP VIEW
(Not to Scale)
36 NC
35 PDO1
34 PDO2
33 PDO3
32 PDO4
31 PDO5
30 PDO6
29 PDO7
28 PDO8
27 PDO9
26 PDO10
25 NC
13 14 15 16 17 18 19 20 21 22 23 24
Figure 3. LFCSP Pin Configuration
NC = NO CONNECT
Figure 4. TQFP Pin Configuration
Table 2. Pin Function Descriptions
Pin No.
LFCSP TQFP
Mnemonic Description
1, 12–13, NC
24–25,
36–37, 48
No connection.
1–5 2–6
VX1–5
High Impedance Inputs to Supply Fault Detectors. Fault thresholds can be set from 0.573 V to 1.375 V.
Alternatively, these pins can be used as general-purpose digital inputs.
6–9 7–10
VP1–4
Low Voltage Inputs to Supply Fault Detectors. Three input ranges can be set by altering the input
attenuation on a potential divider connected to these pins, the output of which connects to a supply
fault detector. These pins allow thresholds from 2.5 V to 6.0 V, 1.25 V to 3.00 V, and 0.573 V to 1.375 V.
10
11
VH
High Voltage Input to Supply Fault Detectors. Three input ranges can be set by altering the input
attenuation on a potential divider connected to this pin, the output of which connects to a supply
fault detector. This pin allows thresholds from 6.0 V to 14.4 V and 2.5 V to 6.0 V.
11
14
AGND
Ground Return for Input Attenuators.
12
15
REFGND Ground Return for On-Chip Reference Circuits.
13
16
REFIN
Reference Input for ADC. Nominally, 2.048 V.
14
17
REFOUT
2.048 V Reference Output.
15–20 18–23
DAC1–6
Voltage Output DACs. These pins default to high impedance at power-up.
21–30 26–35
PDO10–1 Programmable Output Drivers.
31
38
PDOGND Ground Return for Output Drivers.
32
39
VCCP
Central Charge-Pump Voltage of 5.25 V. A reservoir capacitor must be connected between this pin
and GND.
33
40
A0
Logic Input. This pin sets the seventh bit of the SMBus interface address.
34
41
A1
Logic Input. This pin sets the sixth bit of the SMBus interface address.
35
42
SCL
SMBus Clock Pin. Open-drain output requires external resistive pull-up.
36
43
SDA
SMBus Data I/O Pin. Open-drain output requires external resistive pull-up.
37
44
AUX2
Auxiliary, Single-Ended ADC Input.
38
45
AUX1
Auxiliary, Single-Ended ADC Input.
39
46
VDDCAP Device Supply Voltage. Linearly regulated from the highest of the VP1–4, VH pins to a typical of 4.75 V.
40
47
GND
Supply Ground.
Rev. 0 | Page 7 of 32
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