ADM1027ARQ-REEL 查看數據表（PDF） - ON Semiconductor
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ADM1027ARQ-REEL Datasheet PDF : 56 Pages
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ADM1027
Parameter
Min
Typ Max Unit
OPEN-DRAIN SERIAL DATA BUS
OUTPUT (SDA)
Output Low Voltage, VOL
High Level Output Current, IOH
SMBUS DIGITAL INPUTS
(SCL, SDA)
Input High Voltage, VIH
Input Low Voltage, VIL
Hysteresis
0.4
V
0.1
1
mA
2.0
V
0.4
V
500
mV
DIGITAL INPUT LOGIC LEVELS
(VID0–4)
Input High Voltage, VIH
Input Low Voltage, VIL
DIGITAL INPUT LOGIC LEVELS
(TACH INPUTS)
Input High Voltage, VIH
Input Low Voltage, VIL
Hysteresis
1.7
V
0.8
V
2.0
V
5.5
V
0.8
V
–0.3
V
0.5
V p-p
DIGITAL INPUT CURRENT
Input High Current, IIH
Input Low Current, IIL
Input Capacitance, CIN
–1
mA
1
mA
5
pF
SERIAL BUS TIMING
Clock Frequency, fSCLK
10
Glitch Immunity, tSW
Bus Free Time, tBUF
4.7
Start Setup Time, tSU;STA
4.7
Start Hold Time, tHD;STA
4.0
SCL Low Time, tLOW
4.7
SCL High Time, tHIGH
4.0
SCL, SDA Rise Time, tr
SCL, SDA Fall Time, tf
Data Setup Time, tSU;DAT
250
Data Hold Time, tHD;DAT
300
Detect Clock Low Timeout, tTIMEOUT
15
100
kHz
50
ns
ms
ms
ms
ms
50
ms
1000 ns
300
ms
ns
ns
35
ms
NOTES
1All voltages are measured with respect to GND, unless otherwise specified.
2Typicals are at TA = 40rC and represent the most likely parametric norm.
3Logic inputs will accept input high voltages up to VMAX even when the device is operating down to VMIN.
4Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.0 V for a rising edge.
Specifications subject to change without notice.
Test Conditions/Comment
IOUT = –4.0 mA, VCC = 3.3 V
VOUT = VCC
Maximum Input Voltage
Minimum Input Voltage
VIN = VCC
VIN = 0
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
Can Be Optionally Disabled
REV. A
Rev. 3 | Page 3 of 56 | www.onsemi.com
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