N28F001BN-B150 查看數據表（PDF） - Intel
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N28F001BN-B150 Datasheet PDF : 33 Pages
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28F001BX-T 28F001BX-B
Power Supply Decoupling
Flash memory power switching characteristics re-
quire careful device coupling System designers are
interested in 3 supply current issues standby current
levels (ISB) active current levels (ICC) and transient
peaks producted by falling and rising edges of CE
Transient current magnitudes depend on the device
outputs’ capacitive and inductive loading Two-line
control and proper decoupling capacitor selection
will suppress transient voltage peaks Each device
should have a 0 1 mF ceramic capacitor connected
between its VCC and GND and between its VPP and
GND These high frequency low inherent-induc-
tance capacitors should be placed as close as pos-
sible to the device Additionally for every 8 devices
a 4 7 mF electrolytic capacitor should be placed at
the array’s power supply connection between VCC
and GND The bulk capacitor will overcome voltage
slumps caused by PC board trace inductances
VPP Trace on Printed Circuit Boards
Programming flash memories while they reside in
the target system requires that the printed circuit
board designer pay attention to the VPP power sup-
ply trace The VPP pin supplies the memory cell cur-
rent for programming Use similar trace widths and
layout considerations given to the VCC power bus
Adequate VPP supply traces and decoupling will de-
crease VPP voltage spikes and overshoots
VCC VPP RP Transitions and the
Command Status Registers
Programming and erase completion are not guaran-
teed if VPP drops below VPPH If the VPP Status bit of
the Status Register (SR 3) is set to ‘‘1’’ a Clear
Status Register command MUST be issued before
further program erase attempts are allowed by the
WSM Otherwise the Program (SR 4) or Erase
(SR 5) Status bits of the Status Register will be set
to ‘‘1’’ if error is detected RP transitions to VIL
during program and erase also abort the operations
Data is partially altered in either case and the com-
mand sequence must be repeated after normal op-
eration is restored Device poweroff or RP tran-
sitions to VIL clear the Status Register to initial val-
ue 80H
The Command Register latches commands as is-
sued by system software and is not altered by VPP
or CE transitions or WSM actions Its state upon
powerup after exit from Deep-Powerdown or after
VCC transitions below VLKO is FFH or Read Array
Mode
After program or erase is complete even after VPP
transitions down to VPPL the Command Register
must be reset to read array mode via the Read Array
command if access to the memory array is desired
Power Up Down Protection
The 28F001BX is designed to offer protection
against accidental erasure or programming during
power transitions Upon power-up the 28F001BX is
indifferent as to which power supply VPP or VCC
powers up first Power supply sequencing is not re-
quired Internal circuitry in the 28F001BX ensures
that the Command Register is reset to Read Array
mode on power up
A system designer must guard against spurious
writes for VCC voltages above VLKO when VPP is
active Since both WE and CE must be low for a
command write driving either to VIH will inhibit
writes The Command Register architecture provides
an added level of protection since alteration of mem-
ory contents only occurs after successful completion
of the two-step command sequences
Finally the device is disabled until RP is brought
to VIH regardless of the state of its control inputs
This provides an additional level of protection
28F001BX Power Dissipation
When designing portable systems designers must
consider battery power consumption not only during
device operation but also for data retention during
system idle time Flash nonvolatility increases us-
able battery life because the 28F001BX does not
consume any power to retain code or data when the
system is off
In addition the 28F001BX’s Deep-Powerdown mode
ensures extremely low power dissipation even when
system power is applied For example laptop and
other PC applications after copying BIOS to DRAM
can lower RP to VIL producing negligible power
consumption If access to the boot code is again
needed as in case of a system RESET the part
can again be accessed following the tPHAV wakeup
cycle required after RP is first raised back to VIH
The first address presented to the device while in
powerdown requires time tPHAV after RP tran-
sitions high before outputs are valid Further ac-
cesses follow normal timing See AC Characteris-
tics Read-Only Operations and Figure 12 for more
information
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