ADM6308 查看數據表（PDF） - Unspecified

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ADM6308

Eight-port 10/100M Ethernet Switch Controller

Unspecified 

Olive plus Specification

RXDV0

RXDV1

RXDV2

RXDV3

RXDV4

RXDV5

RXDV6

RXDV7

80, 90

98, 5

15, 24

31, 39

5

I Carrier Sense and Receive Data Valid. RXDV2, RXDV3, RXDV5, RDDV6, RXDV7

internally pull down. RXDV0~7 shall be asserted by the PHY when the receiver is not idle.

The specific definition of idle for 10BASE-T and 100BASE-X is contained in IEEE 802.3

and IEEE 802.3u.

RXDV0~7 also shows that the receiving data is presented on the RXD0~7[1:0] from

Reduced MII connecting device. RXDV0~7 is being asserted asynchronous on detection of

carrier due to criteria relevant to the operating mode. That is, in 10BASE-T mode, when

squelch is passed or in 100BASE-X mode when 2 non-contiguous zeroes in 10 bits are

detected, carrier is said to be detected.

Loss of carrier shall result in the de-assertion of RXDV0~7 synchronous to the cycles of

REFCLK which presents the first di-bit of a nibble onto RXD0~7[1:0]. If the PHY has

additional bits to be presented on RXD0~7[1:0] following the initial de-assertion of

RXDV0~7, then the PHY shall assert RXDV0~7 on cycles of REFCLK which present the

second di-bit of each nibble, and de-assert RXDV0~7 on cycles of REFCLK which present

the first di-bit of a nibble. During a false carrier event, RXDV0~7 shall remain asserted for

the duration of carrier activity.

The data on RXD0~7[1:0] is considered valid once RXDV0~7 is being asserted. However,

since the assertion of RXDV0~7 is asynchronous relative to REFCLK, the data on

RXD0~7[1:0] shall be “00” until proper receive signal decoding takes place.

RXD0[1:0]

RXD1[1:0]

RXD2[1:0]

RXD3[1:0]

RXD4[1:0]

RXD5[1:0]

RXD6[1:0]

RXD7[1:0]

82, 81

93, 92

100, 99

8,7

17, 16

26, 25

33, 32

41, 40

I Receive Data. RXD 2[1:0], RXD 3[1:0], RXD 5[1:0], RXD 6[1:0], RXD 7[1:0] internally

pull down. These bundle signals are input from the Reduced MII connecting device.

RXD0~7[1:0] shall transition synchronously to REFCLK. For each clock period in which

RXDV0~7 is being asserted, RXD0~7[1:0] transfers two bits of recovered data from the

PHY. In some cases (e.g. before data recovery or during error conditions) a pre-determined

value for RXD0~7[1:0] is transferred instead of the recovered data. RXD0~7[1:0] shall be

“00” to indicate idle when RXDV0~7 is de-asserted. Values of RXD0~7[1:0] other than

“00” when RXDV0~7 as recovered from RXDV0~7 is de-asserted are reserved for out-of-

band signaling (to be defined). Values other than “00”on RXD0~7[1:0] while RXDV0~7 as

recovered from RXDV0~7 is de-asserted shall be ignored by the MAC. Upon assertion of

RXDV0~7, the PHY shall ensure that RXD0~7[1:0]=”00”until proper receive decoding

takes place.

These pins will be in high impedance, and ignore the input when RXDV0~7 is negative.

RXC0

RXD0[3:2]

CRS0

COL0

MII#

79 BI Receive Clock for port0 MII mode.

4ma

84, 83 BI Receive Data. RXD 0[3:2] internally pull down for port0 MII mode..

4ma

69 BI Carrier Sense for port0 MII mode.

4ma

70 BI Collision for port0 MII mode.

4ma

67

I Internally pull up. Active low. This pin can be tied to low for reversing the Reduced MII to

MII (port0 only). There is an internal pull high for default configuration.

ADM6308 also provides the 1MII+7RMII mode for customer specific requirement. The

default address IDs for PHY are the consecutive numbers as follows: 7(for port 0 MII), 8, 9,

10, 11,12,13,14,(for port 1~7 RMII).

P.S.: The ID addresses must be the consecutive numbers, otherwise, ADM6308 won’t

recognize the ID address for PHY.

ADMtek Incorporated

00/04/25

1F, No 9, Industrial E. 9th Road, SBIP, Hsin-Chu

Version : 1.10

Tel : (03)578-8879 Fax : (03)578-8871

ADMtek Incorporated Confidential

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