ADM6820ARJZ-REEL7 查看數據表（PDF） - Analog Devices

零件编号

产品描述 (功能)

生产厂家

ADM6820ARJZ-REEL7

FET Drive Simple Sequencers®

Analog Devices 

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

ADM6819/ADM6820

VCC1 1

6 VCC2

ADM6819

GND 2 TOP VIEW 5 GATE

(Not to Scale)

SETV 3

4 EN

Figure 6. ADM6819 Pin Configuration

VCC1 1

6 VCC2

ADM6820

GND 2 TOP VIEW 5 GATE

(Not to Scale)

SETV 3

4 SETD

Figure 7. ADM6820 Pin Configuration

Table 4. Pin Function Descriptions

Pin Number

ADM6819 ADM6820 Mnemonic

1

1

VCC1

2

2

GND

3

3

SETV

4

–

EN

–

4

SETD

5

5

GATE

6

6

VCC2

Description

Supply Voltage 1. Either VCC1 or VCC2 must be greater than the UVLO to enable external

FET Drive.

Chip Ground Pin.

Sequenced Threshold Set. Connect to an external resistor divider to set the VCC1

threshold that enables GATE turn-on. The internal reference is 0.618 V.

Active-High Enable. GATE drive is enabled tDELAY after EN is driven high. GATE drive is

immediately disabled when EN is driven low. Connect this pin to the higher of VCC1 or

VCC2 if not used. EN is internally identical to SETV (0.618 V threshold) and, therefore, can

be used as a second supply monitor, enabling two supplies to be validated before

sequencing begins.

GATE Delay Set Input. Connect an external capacitor from SETD to GND to adjust the

delay from SETV > VTH to GATE turn-on. tDELAY(s) = 2.652 × 106 × CSET(F).

GATE Drive Output. GATE drives an external N-channel FET to connect VCC2 to the load.

GATE drive enables tDELAY after SETV exceeds VTH and ENABLE is driven high. GATE drive is

immediately disabled when SETV drops below VTH or ENABLE is driven low. When

enabled, an internal charge pump drives GATE above VCCX to fully enhance the external

N-channel FET.

Supply Voltage 2. Either VCC1 or VCC2 must be greater than the UVLO to enable the

external FET Drive.

Rev. 0 | Page 7 of 12

Share Link: