ADM8832(RevB) 查看數據表（PDF） - Analog Devices
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ADM8832 Datasheet PDF : 12 Pages
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ADM8832
Data Sheet
THEORY OF OPERATION
SCANNING AND BLANKING
TRANSIENT RESPONSE
A TFT LCD panel is made up of a bank of capacitors, each
representing a pixel in the display. These capacitors store
different levels of charge, depending on the amount of
luminescence required for a given pixel. When a picture is
displayed on the panel, a scan of all the pixel capacitors is
performed, placing different levels of charge on each in order to
create the image. The process of updating the display like this is
called scanning. Once scanned, an image is held by pixel
The ADM8832 features extremely fast transient response,
making it very suitable for fast image updates on TFT LCD
panels. This means that even under changing load conditions
there is still very effective regulation of the 5 V output. Figure 12
and Figure 13 show how the 5.1 V output responds when a
maximum load is dynamically connected and disconnected.
Note that the output settles within 5 μs to less than 1% of the
output level.
capacitance, and the controller and source line drivers can be
put into a low power mode. This low power mode is referred to
as the blanking mode on the ADM8832. Over a finite period of
time, this pixel charge will leak and the capacitors will need to
be refreshed in order to maintain the image.
E The ADM8832 uses scanning and blanking modes, as follows.
When the TFT LCD panel is in scanning mode, a logic high on
the SCAN/BLANK input places the device in high current
T power mode, providing extra power (extra current) to the LCD
controller and the source line drivers. If the panel continues to
be updated (as when a moving picture is being displayed), the
ADM8832 can be continually operated in scanning mode. If the
E same image is kept on the panel, a logic low is applied to the
SCAN/BLANK input, and the ADM8832 enters blanking (low
current) mode. Depending on how often the image is updated,
L the ADM8832 can be operated with a variable SCAN/ BLANK
duty cycle. This helps to maximize power efficiency and,
therefore, extends the battery life.
POWER SEQUENCING
O The gate drive supplies must be sequenced such that the −10 V
supply is up before the +15 V supply for the TFT panel to power
on correctly. The ADM8832 controls this sequence. When the
S device is turned on (a logic high on SHDN), the ADM8832
allows the −10 V output to ramp immediately, but holds off the
+15 V output. It continues to do this until the negative output
reaches −3 V. At this point, the positive output is enabled and
B allowed to ramp up to +15 V. This sequence is shown in Figure 17.
VCC
O SHDN
tR5V
EXTERNAL CLOCK
The ADM8832 has an internal 100 kHz oscillator, but an
external clock source can also be used to clock the part. This
clock source must be applied to the CLKIN pin. Power is saved
during blanking periods by disabling the internal oscillator and
by switching to the lower frequency external clock source. To
achieve optimum performance of the charge pump circuitry, it
is important that the duty cycle of the external clock source is
50% and that the rise and fall times are less than 20 ns.
90%
10%
tR
tF
tH
tT
tR: RISE TIME
tF: FALL TIME
tH
tT
@
100% =
DUTY CYCLE
Figure 18. Duty Cycle of External Clock
0.280
0.400
+5V
tR15V
90%
10%
tF5V
+15V
tR15V
–10V
90%
–3V
10%
tF10V
LOAD
tF15V
tR10V
0.875
SOLDER MASK
BOARD METALLIZATION
0.200
0.250
Figure 19. Suggested LFCSP 4 mm × 4mm 20 Lead Land Pattern
SCAN/BLANK
EXTERNAL
CLOCK
Figure 17. Power Sequence
Rev. B | Page 10 of 12
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