ADN2811 查看數據表（PDF） - Analog Devices

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ADN2811

OC-48/OC-48 FEC Clock and Data Recovery IC with Integrated Limiting Amp

Analog Devices 

ADN2811

Parameter

Conditions

Min

Setup Time

TS (See Figure 3) OC-48

140

Hold Time

TH (See Figure 3) OC-48

150

REFCLK DC INPUT CHARACTERISTICS

Input Voltage Range

@ REFCLKP or REFCLKN

0

Peak-to-Peak Differential Input

100

Common-Mode Level

DC-Coupled, Single-Ended

TEST DATA DC INPUT CHARACTERISTICS4 (TDINP/N) CML Inputs

Peak-to-Peak Differential Input Voltage

LVTTL DC INPUT CHARACTERISTICS

Input High Voltage

VIH

2.0

Input Low Voltage

VIL

Input Current

VIN = 0.4 V or VIN = 2.4 V

−5

LVTTL DC OUTPUT CHARACTERISTICS

Output High Voltage

VOH, IOH = −2.0 mA

2.4

Output Low Voltage

VOL, IOL = +2.0 mA

1 PIN and NIN should be differentially driven, ac-coupled for optimum sensitivity.

2 PWD measurement made on quantizer outputs in Bypass mode.

3 Measurement is equipment limited.

4 TDINP/N are CML inputs. If the drivers to the TDINP/N inputs are anything other than CML, they must be ac-coupled.

Typ Max

Unit

ps

ps

VCC

V

mV

VCC/2

V

0.8

V

V

0.8

V

+5

µA

V

0.4

V

Rev. B | Page 4 of 20

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