ADN2817ACPZ-RL7(RevG) 查看數據表（PDF） - Analog Devices

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ADN2817ACPZ-RL7
(Rev.:RevG)

Continuous Rate 10 Mbps to 2.7 Gbps Clock and Data Recovery ICs

Analog Devices 

ADN2817/ADN2818

Data Sheet

Table 10. Control Register, CTRLA

fREF Range

D7

D6

Range

Set to 0 Set to 0 10 MHz to 25 MHz

Set to 0 Set to 1 25 MHz to 50 MHz

Set to 1 Set to 0 50 MHz to 100 MHz

Set to 1 Set to 1 100 MHz to 200 MHz

Data Rate/DIV_FREF Ratio

D5 D4 D3 D2 Ratio

00001

00012

00104

n

2n

1 0 0 0 256

Measure Data Rate

D1

Set to 1 to measure data rate

Lock to REFCLK

D0

0 = lock to input data

1 = lock to reference clock

Table 11. Control Register, CTRLB

Config LOL

Reset MISC[4]

Initiate Freq Acquisition

Reset MISC[2]

D7

D6

D5

D4 D3

D2 D1 D0

0 = LOL pin normal

operation

1 = LOL pin is static LOL

Write a 1 followed Write a 1 followed

by 0 to reset MISC[4] by 0 to initiate a

frequency acquisition

Set Write a 1 followed Set Set Set

to 0 by 0 to reset MISC[2] to 0 to 0 to 0

Table 12. Control Register, CTRLC

D7

Set to 0

D6

Set to 0

D5

Set to 0

D4

Set to 0

D3

Set to 0

Configure LOS

D2

0 = active high LOS

1 = active low LOS

Squelch Mode

D1

0 = squelch CLK and DATA

1 = squelch CLK or DATA

D0

Set to 0

Table 13. Control Register, CTRLD

CDR Bypass

Disable

DATAOUT Buffer

D7

D6

0 = CDR enabled 0 = data buffer enabled

1 = CDR disabled 1 = data buffer disabled

Disable

CLKOUT Buffer

D5

0 = CLK buffer enabled

1 = CLK buffer disabled

D4

Set to 0

Initiate PRBS

Sequence

D3

Write a 1 followed

by 0 to initiate a

PRBS generate

sequence

PRBS Mode

D2 D1 D0 Function

0 0 0 Power-down PRBS

0 0 1 Generate mode

1 0 0 Detect mode

Table 14. Control Registers, CTRLE/BERCTLB

Enable BERMON BER Stdby Mode

D7

D6

D5

D4

Set to 0 Set to 0 1 = BERMON

enabled

1 = place BERMON in low

power standby mode

0 = BERMON

disabled

0 = BERMON ready

D3

Set to 0

PRBS/DDR Enable and Output Mode

D2 D1 D0 Function

0 0 0 Normal data rate output mode

0 0 1 Offset decision circuit (ODC) output

mode

0 1 0 Enable DDR mode (double data rate

mode)

0 1 1 Offset decision circuit (ODC) output

in DDR mode

1 0 1 Enable PRBS detector/generator

All other combinations reserved

Rev. G | Page 16 of 38

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