HDNS-2200-001 查看數據表（PDF） - HP => Agilent Technologies
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HDNS-2200-001 Datasheet PDF : 12 Pages
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PS/2 Mode Output Waveforms @ 24 MHz
Host Sending Data Timing Diagram
I/O
INHIBIT
CLK
1ST
CLK
2ND
CLK
DATA
T1
T2
T3
START BIT
(1)
BIT 0
(2)
9TH
CLK
10TH
CLK
11TH
CLK
(5)
(3)
PARITY BIT STOP
BIT
(2)
(4)
Notes:
1. The mouse checks the DATA line. If the line is low, the system has data to transmit. The DATA line is set inactive when the start bit (always 0) is
placed on the DATA line.
2. The mouse samples the DATA line for each bit while the CLK line is high. Data must be stable within 1 microsecond after the rising edge of the
CLK line.
3. The mouse checks for a high stop bit after the 10th CLK. If the DATA line is low, the mouse continues to clock until the DATA line becomes high,
then clocks the line-control bit, and at the next opportunity sends a Resend command to the system.
4. The mouse pulls the DATA line low, producing the line-control bit.
5. The host can pull the CLK line low, inhibiting the mouse.
Timing Parameter
T1
T2
T3
Description
Duration of CLK high
Duration of CLK low
Time from falling CLK transition, to date transition
Min. Time
22.5 µsec
22.5 µsec
0 µsec
Max. Time
37.5 µsec
37.5 µsec
22.5 µsec
Host Receiving Timing Diagram
1ST
CLK CLK
2ND
CLK
T3
T4
T1
T2
DATA START BIT
BIT 0
3RD
CLK
BIT 1
10TH
CLK
11TH
CLK
(1, 2)
BIT 2
T5
PARITY BIT
STOP BIT
Notes:
1. The host can hold the clock signal low to inhibit the next transmission.
2. The host raises the clock line to allow the next transmission.
3. All times given below assume a 24 MHz resonator and are dependent upon its accuracy.
Timing Parameter
T1
T2
T3
T4
T5
Description
Time from DATA transition to falling edge of CLK
Time from rising edge of CLK to DATA transition
Duration of CLK low
Duration of CLK high
Time to mouse inhibit after clock 11 to ensure the
mouse does not start another transmission
9
Min. Time
3.75 µsec
3.75 µsec
22.5 µsec
22.5 µsec
0 µsec
Max. Time
18.75 µsec
18.75 µsec
37.5 µsec
37.5 µsec
37.5 µsec
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