ADN4600-EVALZ 查看數據表（PDF） - Analog Devices

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ADN4600-EVALZ

4.25 Gbps, 8 × 8, Asynchronous Crosspoint Switch

Analog Devices 

ADN4600

TIMING SPECIFICATIONS

Table 2. I2C Timing Parameters

Parameter

Min

Max

fSCL

0

400

tHD;STA

0.6

N/A

tSU;STA

0.6

N/A

tLOW

1.3

N/A

tHIGH

0.6

N/A

tHD;DAT

0

N/A

tSU;DAT

10

N/A

tr

1

300

tf

1

300

tSU;STO

0.6

N/A

tBUF

1

N/A

CIO

5

7

Unit

Description

kHz

SCL clock frequency

μs

Hold time for a start condition

μs

Setup time for a repeated start condition

μs

Low period of the SCL clock

μs

High period of the SCL clock

μs

Data hold time

ns

Data setup time

ns

Rise time for both SDA and SCL

ns

Fall time for both SDA and SCL

μs

Setup time for a stop condition

ns

Bus-free time between a stop and a start condition

Pf

Capacitance for each I/O pin

I2C Timing Specifications

SDA

tf

SCL

S

tLOW

tSU:DAT

tf

tHD:STA

tHD:DAT

tf

tHD:STA

tHIGH

tSU:STA

Sr

Figure 2. I2C Timing Diagram

tf

tBUF

tSU:STO

P

S

Rev. 0 | Page 5 of 5

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