ADN4605(Rev0) 查看數據表（PDF） - Analog Devices
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ADN4605 Datasheet PDF : 56 Pages
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ADN4605
I2C TIMING SPECIFICATIONS
SDA
tf
tLOW
tr
tSU;DAT
tf
tHD;STA
tSP
tr
tBUF
SCL
tHD;STA
S
tHD;DAT
tHIGH
tSU;STA
Sr
Figure 2. I2C Timing Diagram
Table 2. I2C Timing Specifications
Parameter
SCL Clock Frequency
Hold Time for a Start Condition
Setup Time for a Repeated Start Condition
Low Period of the SCL Clock
High Period of the SCL Clock
Data Hold Time
Data Setup Time
Rise Time for Both SDA and SCL
Fall Time for Both SDA and SCL
Setup Time for Stop Condition
Bus Free Time Between a Stop Condition and a Start Condition
Bus Idle Time After a Reset
Reset Pulse Width
Symbol
fSCL
tHD; STA
tSU; STA
tLOW
tHIGH
tHD; DAT
tSU; DAT
tr
tf
tSU; STO
tBUF
tSU;STO
Min
0
0.5
0.5
0.6
0.02
0.02
1
1
0.5
1
20
20
SPI TIMING SPECIFICATIONS
CS
t1
t2
SCLK
DIN
t3
t5
t6
D7 D6 D5 D4 D3 D2 D1 D0 X
X
X
X
X
X
X
DOUT
t4
X
X
X
X
X
X
X
X D7 D6 D5 D4 D3 D2 D1
Figure 3. SPI Timing Diagram
Table 3. SPI Timing Specifications
Parameter
SCK Clock Frequency
CS to SCLK Setup Time
SCLK High Pulse Width
SCLK Low Pulse Width
Data Access Time After SCLK Falling Edge
Data Setup Time Prior to SCLK Rising Edge
Data Hold Time After SCLK Rising Edge
CS to SCLK Hold Time
CS to SDO High Impedance
Reset Pulse Width
Symbol
Min
fSCK
t1
0
t2
30
t3
30
t4
t5
10
t6
30
t7
0
t8
20
P
S
Max
Unit
500+
kHz
μs
μs
1.4
μs
μs
μs
μs
300
ns
300
ns
μs
ns
ns
ns
t7
X
t8
D0
Max
Unit
10
MHz
ns
ns
ns
45
ns
ns
ns
ns
45
ns
ns
Rev. 0 | Page 5 of 56
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