ADN4612 查看數據表（PDF） - Analog Devices

零件编号

产品描述 (功能)

生产厂家

ADN4612

11.3 Gbps, 12 × 12 Digital Crosspoint Switch

Analog Devices 

ADN4612

Data Sheet

SPECIFICATIONS

VCC = VTTO1 = 2.5 V, VTTI2 = V1P8 = DVCC = 1.8 V, VEE = 0 V, RL = 50 Ω, data rate = 11.3 Gbps, data pattern = PRBS 15, ac-coupled inputs

and outputs, differential input swing = 800 mV p-p, EQ setting = 0x12,3 PE boost = 1.94 dB,4 unless otherwise noted.

INPUT/OUTPUT SPECIFICATIONS

Table 1.

Parameter

DYNAMIC PERFORMANCE

Data Rate (NRZ)

Deterministic Jitter (No Channel)

Random Jitter (No Channel)

Residual Deterministic Jitter with

Receive Equalization

Residual Deterministic Jitter with

Transmit Preemphasis

Propagation Delay

Lane-to-Lane Skew

Switching Time

Output Rise/Fall Time

INPUT CHARACTERISTICS

Differential Input Voltage Swing

Input Voltage Range

Differential Input Return Loss (SDD11)

OUTPUT CHARACTERISTICS

Output Voltage Swing

Output Voltage Range

Output Voltage Setting Resolution

Per Port Output Current

Differential Output Return Loss (SDD22)

TERMINATION CHARACTERISTICS

Resistance

LOS CHARACTERISTICS

Assert Level

Deassert Level

LOS-to-Output Squelch

LOS-to-Output Enable

Test Conditions/Comments

Data rate = 10.3125 Gbps

Data rate = 11.3 Gbps

Input trace = 25-inch FR408, data rate = 10.3125 Gbps,

EQ setting = 0x94

Input trace = 15-inch FR408, data rate = 11.3 Gbps,

EQ setting = 0x72

Output trace = 15-inch FR408, data rate = 10.3125 Gbps,

PE boost = 5.46 dB

Output trace = 10-inch FR408, data rate = 11.3 Gbps,

PE boost = 6.02 dB

50% input to 50% output (maximum EQ)

Signal path and switch architecture is balanced and

symmetric (maximum EQ)

50% logic switching to 50% output data5

20% to 80%, test pattern = 0000000011111111

VICM6 = 1.8 V, VCC = VMIN to VMAX, TA = TMIN to TMAX

Single-ended absolute voltage level, VIL minimum

Single-ended absolute voltage level, VIH maximum

At 2.125 GHz

At 5.5 GHz

Differential; PE boost = 0 dB; default output level, at dc

Single-ended absolute voltage level, VOL

Single-ended absolute voltage level, VOH

Differential absolute voltage level minimum step size,

Tx driver resolution bits = 11b (divide by 8)

PE boost = 0 dB, default output level

At 2.125 GHz

At 5.5 GHz

Differential, VCC = VMIN to VMAX, TA = TMIN to TMAX

Programmable; LOS_ASSERT = 0x2

Programmable; LOS_DEASSERT = 0x6

Time from active signal to idle

Time from idle to active signal

Min

DC

<200

660

90

Typ

Max Unit

11.3 Gbps

11

ps p-p

14

ps p-p

0.5

ps rms

0.25

UI

0.25

UI

0.24

UI

0.31

UI

520

ps

±40

ps

10

ns

44

ps

1.0

VCC + 0.3

−24

−10

2000

mV p-p diff

V

V

dB

dB

780

936

VCC − 1.2

VTTO1

12.5

mV p-p diff

V

V

mV p-p diff

16

mA

−20

dB

−9

dB

100

110 Ω

74

mV p-p diff

133

mV p-p diff

1.1

ns

31

ns

1 VTTO is a generic variable that describes both VTTON and VTTOS. VTTON and VTTOS are independent voltages that are not required to equal each other.

2 VTTI is a generic variable that describes both VTTIE and VTTIW. VTTIE and VTTIW are independent voltages that are not required to equal each other.

3 Default EQ setting is used to compensate for loss of test fixture.

4 Default PE setting is used to compensate for loss of test fixture.

5 50% logic level high-to-low transition of the UPDATE toggle pin or 50 % logic level transition of the MAP1 and MAP0 pins while the UPDATE pin is held at logic low.

6 VICM is the input common-mode voltage.

Rev. C | Page 4 of 76

Share Link: