ADN4670 查看數據表（PDF） - Analog Devices

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ADN4670

Programmable Low Voltage 1:10 LVDS Clock Driver

Analog Devices 

ADN4670

Data Sheet

LVDS SWITCHING CHARACTERISTICS

VDD = 2.375 V to 2.625 V; all specifications TMIN to TMAX, unless otherwise noted.

Table 3.

Parameter

Propagation Delay Low to High

Propagation Delay High to Low

Duty Cycle

Output Skew2

Pulse Skew3

Part-to-Part Output Skew4

Output Rise Time

Output Fall Time

Maximum Input Frequency

Symbol

tPLHx

tPHLx

tDUTY

tSK(O)

tSK(P)

tSK(PP)

tr

tf

fCLK

Min

45

900

Typ

2

2

30

1100

Max1 Unit Conditions/Comments

3

ns From CLK0/CLK0 or CLK1/ CLK1 to any Qx/Qx

3

ns From CLK0/CLK0 or CLK1/ CLK1 to any Qx/Qx

55 % From CLK0/CLK0 or CLK1/ CLK1 to any Qx/Qx

ps Any Qx/Qx

50 ps Any Qx/Qx

600 ps Any Qx/Qx

350 ps Any Qx/Qx, 20% to 80%, RL = 100 Ω CL = 5 pF

350

Any Qx/Qx, 80% to 20%, RL = 100 Ω CL = 5 pF

MHz From CLK0/CLK0 or CLK1/ CLK1 to any Qx/Qx

1 Guaranteed by design and characterization.

2 Output skew is defined as the difference between the largest and smallest values of TPLHx within a device or the difference between the largest and smallest values of

TPHLx within a device, whichever of the two is greater.

3 Pulse skew is defined as the magnitude of the maximum difference between tPLH and tPHL for any channel of a device, that is, |tPHLx – tHLPx|.

4 Part-to-part output skew is defined as the difference between the largest and smallest values of TPLHx across multiple devices or the difference between the largest and

smallest values of TPHLx across multiple devices, whichever of the two is greater.

CLK

CLK

Q0

Q0

Q1

Q1

tPLH0

tPLH1

tPHL0

tPHL1

Q9

Q9

tPLH9

tPHL9

Figure 2. Waveforms for Calculation of tSK(O) and tSK(PP)

Rev. A | Page 4 of 12

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