ADN4670 查看數據表（PDF） - Analog Devices

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ADN4670

Programmable Low Voltage 1:10 LVDS Clock Driver

Analog Devices 

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

ADN4670

CK 1

SI 2

CLK0 3

CLK0 4

VBB 5

CLK1 6

CLK1 7

EN 8

ADN4670

TOP VIEW

(Not to Scale)

24 Q3

23 Q3

22 Q4

21 Q4

20 Q5

19 Q5

18 Q6

17 Q6

NOTES

1. THE EXPOSED PAD CAN BE CONNECTED

TO GROUND OR LEFT FLOATING.

Figure 4. Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic Description

1

CK

Programming Clock. Programming data is clocked in on a low-to-high transition at this input. If left

open-circuit, it is pulled high by a 120 kΩ resistor.

2

SI

Serial Data Input. This is the input for programming data. If left open-circuit, it is pulled low by a 120 kΩ

resistor.

3

CLK0

Noninverting Differential Clock Input 0.

4

CLK0

Inverting Differential Clock Input 0.

5

VBB

Reference Voltage Output.

6

CLK1

Noninverting Differential Clock Input 1.

7

CLK1

Inverting Differential Clock Input 1.

8

EN

Active-High Enable Input. When this input is high, programming is enabled. If left open-circuit, it is

pulled low by a 120 kΩ resistor.

9, 25

VSS

Device Ground.

10, 12, 14, 17, 19, Q9 to Q0

21, 23, 26, 28, 30

Inverted Clock Output. When the differential input voltage is between CLKx and CLKx > 100 mV, this

output sinks current. When the differential input voltage is between CLKx and CLKx < −100 mV, this

output sources current.

11, 13, 15, 18, 20, Q9 to Q0

22, 24, 27, 29, 31

Noninverted Clock Output. When the differential input voltage is between CLKx and CLKx > 100 mV,

this output sources current. When the differential input voltage is between CLKx and CLKx < −100 mV,

this output sinks current.

16, 32

VDD

Power Supply Input. This part can be operated from 2.375 V to 2.625 V.

Rev. A | Page 7 of 12

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