ADP3088 查看數據表（PDF） - Analog Devices
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ADP3088 Datasheet PDF : 11 Pages
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PRELIMINARY TECHNICAL DATA
tor of reasonable quality, the pole setting capacitor could
be chosen to be CHF = 4.7 pF.
A general purpose application circuit is shown in Figure 2.
5V
1µF
MLCC
CHF
4.7pF
ADP3088
IN
SW
IN
DRV
GND GND
COMP FB
CC
470pF
RC
10kΩ
6.8µH
1A
10µF
SCHOTTKY MLCC
VOUT
1.5V
RA
10kΩ
RB
48.7kΩ
Figure 2. +5 V to 1.5 V, General Purpose Application
Another application circuit features a voltage inversion and
regulation design such that the output voltage is negative,
see Figure 3. Negative output voltages are allowed in the
case that the input plus the output voltage does not exceed
the rating of the device. In the voltage inverting configura-
tion, the ground reference of the ADP3088 is the negative
output voltage and the conventional output voltage point is
tied to ground. Operation is bootstrapped: the power con-
verter behaves as if the input voltage were equal to the
actual input voltage plus the magnitude of the output volt-
age and as if the output voltage were not inverted. This
implies that it is possible to have the input voltage be less
than the magnitude of the output voltage - provided that
the input voltage alone is sufficient to start the operation of
the IC - i.e., before the negative output voltage has been
developed. (The circuit below with a -3.3V output works
fine over an input range from 2.5 V to 7.5 V.) Since the
ADP3088 features a current controlled loop, the feedback
effect of essentially boosting the input voltage atop the out-
put (with respect to the ground connection of the
ADP3088) is reduced to a negligible second-order effect.
5V
1µF
MLCC
CHF
4.7pF
ADP3088
IN
SW
IN
DRV
GND GND
COMP FB
CC
220pF
RC
20kΩ
4.7µH
1A
10µF
SCHOTTKY MLCC
+
RA
10kΩ
+
RB
3.04kΩ
-3.3V
Figure 3. +5V to -3.3V, General Purpose Inverting
Application
Voltage Positioning Designs
For digital loads a different compensation technique is rec-
ommended that involves implementing "voltage position-
ing", that is now commonly used on CPUs but is equally
applicable to any dynamic device. Voltage positioning is the
intentional and controlled variation of output voltage with
load current, such that the power supply appears to have a
substantial output resistance. The key to voltage positioning
optimization for a digital load is to degenerate the loop gain
ADP3088
just enough so that the static load regulation allows a similar
voltage deviation with current as would be the peak voltage
deviation, ∆VO, that could not be avoided in the event that
a step change of current were to occur even if the loop
response were instantaneous. The reason for even an in-
stantaneous response in the control loop allowing an output
voltage deviation is that the slew-rate of current in the out-
put is limited by to the inductor, and a corresponding dy-
namic burden is placed on the output capacitor to maintain
the output voltage. Therefore, inductor value minimization
is desired both for concern of its size and cost, and also to
maximize the slew rate of current to the output so that a
smaller output capacitor is needed.
To implement voltage positioning, a resistor, RFB, should
be placed between the COMP and FB pins according to the
formula:
RFB
=
∆IORA
gMOD × ∆VO
(17)
where gMOD is the modulator gain and ∆IO must be assessed
over the entire operating load range as the difference be-
tween maximum and minimum load. CO must be chosen at
least large enough to support the targeted ∆VO according to
the earlier stated formula governing the relationship be-
tween minimum output capacitance, voltage deviation, and
load current. In order to ensure that the output voltage will
be constrained within the limitations of ∆VO, the limitations
noted earlier for PSM hysteretic ripple if applicable in the
operating load range and ESR. Also an experimental ad-
justment downward to the value of RB may be needed, as
the DC bias point of the COMP node is usually a little
higher than VREF, which would result in a slight downward
shift of the nominal output voltage.
Having chosen this design approach, the series RC of the
compensation network can be removed and the single re-
maining capacitor, CHF, should be increased to approxi-
mately:
CHF
=
CO × ESR
RFB
(18)
If an MLC capacitor is used for CO, the value of CHF might
be calculated to be less than a few picofarads, in which case
it is recommended to use a 4.7~10 pF capacitor. The for-
mula is derived from a patented design technique called
ADOPTTM - Analog Devices' Optimal Positioning Tech-
nology. This creates AC and DC impedance matching,
and the increased complexity of the DC regulation design is
moderated by the simplicity of the frequency compensa-
tion.
In this design approach, at higher currents the output volt-
age will be appreciably lower than at low currents. This is
equivalent to saying that the load regulation appears to be
poor. But, paradoxically perhaps to the user unfamiliar with
voltage positioning, the overall containment of voltage
within a given window will be improved, and that tends to
be of particularly importance in many highly dynamic
loads.
The application circuit in Figure 4 features a 3.3 V input
and a 2.5 V output at 100~400 mA which constrains the
REV. PrK
–9–
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