ADP3204 查看數據表（PDF） - Analog Devices

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ADP3204

3-Phase IMVP-II and IMVP-III Core Controller for Mobile CPUs

Analog Devices 

ADP3204–SPECIFICATIONS1(0°C Յ TA Յ 100°C, High (H) = VCC, Low (L) = 0 V, VCC = 3.3 V, SD = H, VCOREFB =

VDAC (VDACOUT), VREG = VCS– = VVID = 1.25 V, CDACRAMP = 100 pF, ROUT1 = ROUT2 = ROUT3 =

100 k⍀, COUT1

DPRSHIFT are

o=peCnOU,TB2 O=MC=OUTH3,=D1P0SLpPF,=CSHS,

= 0.047 ␮F, RPWRGD

DPRLP = L, unless

= 680 ⍀

otherwise

to 1.2 V, RCLAMP = 5.1

noted.) Current sunk

k⍀ to VCC, HYSSET, BSHIFT,

by a pin has a positive sign,

DSHIFT,

sourced

and

by a

pin

has

a

negative sign. Negative sign is disregarded for min and max values.

Parameter

SUPPLY-UVLO-SHUTDOWN

Normal Supply Current

UVLO Supply Current

Shutdown Supply Current

Symbol

ICC

ICCUVLO

ICCSD

UVLO Threshold

VCCH

VCCL

UVLO Hysteresis

Shutdown Threshold

(CMOS Input)

POWER GOOD

Core Feedback Threshold Voltage

VCCHYS

VSDTH

VCOREFBH

Power Good Output Voltage

(Open-Drain Output)

Masking Time2

SOFT START/HICCUP TIMER

Charge/Discharge Current

Soft Start Enable/Hiccup

Termination Threshold

Soft Start Termination/Hiccup

Enable Threshold

VID DAC

VID Input Threshold

(CMOS Inputs)

VID Input Current

(Internal Active Pull-Up)

Output Voltage

Accuracy

VPWRGD

tPWRGDMSK3

ISS

VSSEN

VSSTERM

VVID0..4

IVID0..4

VDAC

⌬VDAC/VDAC

Settling Time

DACRAMP Inner Resistance5

tDACS4

RDACRAMP

Conditions

Min Typ Max

Unit

SD = L, 3.0 V ≤ VCC ≤ 3.6 V

7

11

mA

425

␮A

70

␮A

SD = H

VCC ramping up, VSS = 0 V

2.95

V

VCC ramping down,

2.60

V

VSS floating

55

mV

VCC/2

V

0.9 V < VDAC < 1.675 V

VCOREFB ramping up

VCOREFB ramping down

VCOREFB ramping up

VCOREFB ramping down

VCOREFB = VDACOUT

VCOREFB = 0.8 VDACOUT

1.12 VDAC

1.10 VDAC

0.88 VDAC

0.86 VDAC

0.95 VCC

0

100

1.14 VDAC V

1.12 VDAC V

0.90 VDAC V

0.88 VDAC V

VCC

V

0.8

V

␮s

VSS = 0 V

–55

␮A

VSS = 0.5 V

1.2

␮A

VREG = 1.25 V,

VRAMP = VCOREFB = 1.27 V

VSS ramping down

200 300

mV

VRAMP = VCOREFB = 1.27 V

VSS ramping up

1.70 2.00 2.25

V

VID0 to VID4 = L

VCC/2

V

85

␮A

See VID Code, Table 1

0.600

1.750

V

1.750 V ≥ VDAC ≥ 0.850 V

–1.0

+1.0

%

0.825 V ≥ VDAC ≥ 0.600 V

–8.5

+8.5

mV

CDACRAMP = 100 pF

3.5

␮s

CDACRAMP = 1 nF

25

␮s

10

k⍀

–2–

REV. 0

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