ADP3204 查看數據表（PDF） - Analog Devices
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ADP3204 Datasheet PDF : 16 Pages
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ADP3204
Parameter
SHIFT SETTING
Battery-Shift Current
Battery-Shift Reference Voltage
Symbol
Conditions
IRAMPB, ICS+B
VBSHIFT
VVID = 1.25 V
IBSHIFT = –100 µA, BOM = L
DPSLP = H
Min Typ Max Unit
–92.5 –100 –107.5 mA
VDAC
V
Deep Sleep-Shift Current
Deep Sleep-Shift Reference
Voltage
Deeper Sleep-Shift Current
Deeper Sleep-Shift Reference
Voltage
IRAMPD, ICS+D
VDSHIFT
VVID = 1.25 V
IDSHIFT = –100 µA, BOM = H
DPSLP = L
–92.5
IREGDPR
ICOREFBDPR8
VDPRSHIFT
IDPRSHIFT = –100 µA, DPRSLP = H –90
VVID = 1.25 V,
110
IDPRSHIFT = –100 µA,
DPRSLP = H
–100 –107.5 mA
VDAC
V
–100 –110 µA
130 150
µA
VDAC
V
SHIFT CONTROL INPUTS
BOM Threshold
(CMOS Input)
DPSLP Threshold
(CMOS Input)
DPRSLP Mode Threshold8
(CMOS Input)
VBOM
VDSLP
VDPRSLP
VCC/2
V
VCC/2
V
VCC/2
V
LOW SIDE DRIVE CONTROL
Output Voltage (CMOS Output)
Output Current
VDRVLSD
IDRVLSD
DPRSLP = H
DPRSLP = L
DPRSLP = H, VDRVLSD = 1.5 V
DPRSLP = L, VDRVLSD = 1.5 V
0
0.7 VCC
+0.4
–0.4
0.4
V
VCC
V
mA
mA
OVER/REVERSE VOLTAGE
PROTECTION CORE FEEDBACK
Overvoltage Threshold
Reverse-Voltage Threshold
Output Current
VCOREFB,
9
OVP
VCOREFB,
9
RVP
ICLAMP
VCOREFB
VCOREFB
VCOREFB = 2.2 V, VCLAMP = 1.5 V
(Open-Drain Output)
VCOREFB = VDAC, VCLAMP = 1.5 V
2
2.0
V
–0.3
V
10
µA
6
mA
NOTES
1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.
2 Two test conditions: 1) PWRGD is OK but forced to fail by applying an out-of-the-Core Good-window voltage (V COREFB, BAD = 1.0 V at VVID = 1.25 V setting) to the
COREFB pin right after the moment that BOM or DPRSLP is asserted/de-asserted. PWRGD should not fail immediately only with the specified blanking delay
time. 2) PWRGD is forced to fail (VCOREFB, BAD = 1.0 V at VVID = 1.25 V setting) but gets into the Core Good-window (V COREFB, GOOD = 1.25 V) right after the moment
that BOM or DPRSLP is asserted/de-asserted. PWRGD should not go high immediately only with the specified blanking delay time.
3 Guaranteed by design
4 Measured from 50% of VID code transition amplitude to the point where V DACOUT settles within ± 1% of its steady state value.
5 Measured between DACRAMP and DACOUT pins.
6 40 mVpp amplitude impulse with 20 mV overdrive. Measured from the input threshold intercept point to 50% of the output voltage swing.
7 Measured between the 30% and 70% points of the output voltage swing.
8 DPRSLP circuit meets the minimum 30 ns DPRSLPVR signal assertion requirement; guaranteed by design.
9 COREFB pin has a resistor divider to GND whose resistance is 41.3 k⍀ (typ), guaranteed by design.
–4–
REV. 0
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