HS-32 查看數據表（PDF） - Unspecified
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HS-32 Datasheet PDF : 8 Pages
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®
®
ADS-944
DYNAMIC PERFORMANCE cont.
S/H Acquisition Time
( to ±0.003%FSR, 2.5V step)
Overvoltage Recovery Time
A/D Conversion Rate
DIGITAL OUTPUTS
MIN.
+25°C
TYP.
MAX.
—
85
90
—
200
—
5
—
—
0 to +70°C
MIN.
TYP. MAX.
—
85
90
—
200
—
5
—
—
–55 to +125°C
MIN.
TYP. MAX.
UNITS
—
85
—
200
5
—
90
ns
—
ns
—
MHz
Logic Levels
Logic "1"
Logic "0"
Logic Loading "1"
Logic Loading "0"
Delay, Edge of ENABLE
to Output Data Valid/Invalid
Output Coding
POWER REQUIREMENTS
Power Supply Ranges
+15V Supply
–15V Supply
+5V Supply
–5V Supply
Power Supply Currents
+15V Supply
–15V Supply
+5V Supply
–5.2V Supply
Power Dissipation
Power Supply Rejection
+2.4
—
—
—
—
—
—
—
—
—
—
+2.4
+0.4
—
–4
—
+4
—
—
—
+2.4
—
—
+0.4
—
—
—
–4
—
—
—
+4
—
—
10
—
—
10
—
—
Offset Binary, Complementary Offset Binary, Two's Complement
—
Volts
+0.4
Volts
–4
mA
+4
mA
10
ns
+14.25
–14.25
+4.75
–4.95
—
—
—
—
—
—
+15.0
–15.0
+5.0
–5.2
+36
–55
+155
–167
2.95
—
+15.75
–15.75
+5.25
–5.45
+45
–65
+168
–175
3.3
±0.05
+14.25
–14.25
+4.75
–4.95
—
—
—
—
—
—
+15.0
–15.0
+5.0
–5.2
+36
–55
+155
–167
2.95
—
+15.75
–15.75
+5.25
–5.45
+45
–65
+168
–175
3.3
±0.05
+14.25
–14.25
+4.9
–5.1
—
—
—
—
—
—
+15.0
–15.0
+5.0
–5.2
+36
–55
+155
–167
2.95
—
+15.75 Volts
–15.75
Volts
+5.25
Volts
–5.45
Volts
+45
–65
+168
–175
3.3
±0.05
mA
mA
mA
mA
Watts
%FSR/%V
Footnotes:
All power supplies should be on before applying a start convert pulse. All
supplies and the clock (start convert pulses) must be present during warmup
periods. The device must be continuously converting during this time.
When COMP. BITS (pin 8) is low, logic loading "0" will be –350µA for this pin.
An 80ns wide start convert pulse is used for all production testing. The start
convert pulse should be between 40 – 80ns or 130 – 160ns to ensure proper
operations. The latter range could be used for those applications requiring less
than a 5MHz sampling rate.
Effective bits is equal to:
Full Scale Amplitude
(SNR + Distortion) – 1.76 + 20 log Actual Input Amplitude
6.02
This is the time required before the A/D output is valid after the analog input is
back within its range.
The minimum supply voltages of +4.9V and –5.1V for ±VDD are required for
–55°C operations only. The minimum limits are +4.75V and –4.95V when
operating at +125°C.
Typical +5V and –5.2V current drain breakdowns are as follows:
+5VAnalog = +85mA
+5VDigital = +70mA
+5VTotal = +155mA
–5.2VAnalog = –114mA
–5.2VDigital = –53mA
–5.2VTotal = –167mA
TECHNICAL NOTES
1. Obtaining fully specified performance from the ADS-944
requires careful attention to pc-card layout and power
supply decoupling. The device's analog and digital ground
systems are not connected to each other internally. For
optimal performance, tie all ground pins (4, 6, 11, and 15)
directly to a large analog ground plane beneath the
package. Bypass all power supplies to ground with 4.7µF
tantalum capacitors in parallel with 0.1µF ceramic capaci-
tors. It is very important that the bypass capacitors be
located as close to the unit as possible. Inductors or
ferrite beads can also be used to improve the power supply
filtering. Refer to Figure 4, the ADS-944 Evaluation Board
Schematic, for more details.
2. The ADS-944 achieves its specified accuracies without the
need for external calibration. If required, the device's small
initial offset and gain errors can be reduced to zero using
the adjustment circuitry shown in Figure 2. When using this
circuitry, or any similar offset and gain-calibration hardware,
make adjustments following warmup. To avoid interaction,
always adjust offset before gain.
3. Pin 8 (COMP. BITS) selects the ADS-944's digital output
coding. When a logic "1" is applied to pin 8, the output
coding is complementary offset binary. When pin 8 has a
logic "0" applied, the output coding becomes offset binary.
The MSB output (pin 31) may be used under these condi-
tions to achieve two's complement coding. Pin 8 is TTL-
compatible and can be driven with digital logic for those who
want dynamic control of its function. There is an internal
pull-up resistor on this pin, allowing pin 8 to be either
connected to +5V or left open when a logic "1" is needed.
4. To enable the three-state outputs, apply a logic "0" (low) to
OUTPUT ENABLE (pin 9). To disable, apply a logic "1"
(high) to pin 9.
3
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