ADS-B932 查看數據表（PDF） - Murata Power Solutions

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ADS-B932

16-Bit, 2MHz Sampling A/D Converters

Murata Power Solutions 

®

®

ADS-932

DYNAMIC PERFORMANCE (Cont.)

Overvoltage Recovery Time 

A/D Conversion Rate

MIN.

—

2

+25°C

TYP.

250

—

MAX.

500

—

0 TO +70°C

MIN.

TYP. MAX.

—

250

500

2

—

—

–55 TO +125°C

MIN. TYP.

MAX.

—

250

500

2

—

—

UNITS

ns

MHz

ANALOG OUTPUT

Internal Reference

Voltage

Drift

External Current

3.15

+3.2

3.25

3.15

+3.2

3.25

3.15

+3.2

3.25

Volts

—

±30

—

—

±30

—

—

±30

—

ppm/°C

—

5

—

—

5

—

—

5

—

mA

DIGITAL OUTPUTS

Logic Levels

Logic "1"

Logic "0"

Logic Loading "1"

Logic Loading "0"

Delay, Falling Edge of Enable to

Output Data Valid

Output Coding

POWER REQUIREMENTS

+2.4

—

—

+2.4

—

—

+2.4

—

—

Volts

—

—

+0.4

—

—

+0.4

—

—

+0.4

Volts

—

—

–4

—

—

–4

—

—

–4

mA

—

—

+4

—

—

+4

—

—

+4

mA

—

—

10

—

—

10

—

—

10

ns

Straight Binary, Complementary Binary, Complementary Offset Binary,

Complementary Two's Complement, Offset Binary, Two's Complement

Power Supply Ranges ‘

+5V Supply

–5V Supply

Power Supply Currents

+5V Supply

–5V Supply

Power Dissipation

Power Supply Rejection

+4.75

+5.0

+5.25

–4.75

–5.0

–5.25

—

+225

260

–140

–135

—

—

1.85

2.0

—

—

±0.07

Footnotes:

ΠAll power supplies must be on before applying a start convert pulse. All

supplies and the clock (START CONVERT) must be present during warm-up

periods. The device must be continuously converting during this time. There is

a slight degradation in performance when operating the device in the unipolar

mode.

 When COMP. BITS (pin 35) is low, logic loading "0" will be –350µA.

Ž A 1MHz clock with a positive pulse width is used for all production

testing. See Timing Diagram for more details.

40ns < Start Pulse < 175ns or 280ns < Start Pulse < 460ns

+4.75

+5.0

+5.25

+4.9

+5.0

+5.25

Volts

–4.75

–5.0

–5.25

–4.9

–5.0

–5.25

Volts

—

+225

260

—

+225

260

mA

–140

–135

—

–140

–135

—

mA

—

1.85

2.0

—

1.85

2.0

Watts

—

—

±0.07

—

—

±0.07 %FSR/%V

 Effective bits is equal to:

Full Scale Amplitude

(SNR + Distortion) – 1.76 + 20 log Actual Input Amplitude

6.02

 This is the time required before the A/D output data is valid once the analog

input is back within the specified range. This time is only guaranteed if the input

does not exceed ±4.75V (bipolar)

or +2 to –7.5V (unipolar).

‘ The minimum supply voltages of +4.9V and –4.9V for ±VDD are required for

–55°C operation only. The minimum limits are +4.75V and –4.75V when

operating at +125°C.

TECHNICAL NOTES

1. Obtaining fully specified performance from the ADS-932

requires careful attention to pc-card layout and power supply

decoupling. The device's analog and digital ground systems

are connected to each other internally. For optimal perfor-

mance, tie all ground pins (4, 7, 30 and 36) directly to a

large analog ground plane beneath the package.

Bypass all power supplies and the +3.2V reference output to

ground with 4.7µF tantalum capacitors in parallel with 0.1µF

ceramic capacitors. Locate the bypass capacitors as close

to the unit as possible.

2. The ADS-932 achieves its specified accuracies without the

need for external calibration. If required, the device's small

initial offset and gain errors can be reduced to zero using

the adjustment circuitry shown in Figure 2. When using this

circuitry, or any similar offset and gain calibration hardware,

make adjustments following warm-up. To avoid interaction,

always adjust offset before gain. Tie pins 5 and 6 to

ANALOG GROUND (pin 4) if not using offset and gain adjust

circuits.

3. Pin 35 (COMP. BITS) is used to select the digital output

coding format of the ADS-932 (see Tables 2a and 2b).

When this pin has a TTL logic "0" applied, it complements

all of the ADS-932’s digital outputs.

Pin 35 is TTL compatible and can be directly driven with

digital logic in applications requiring dynamic control over its

function. There is an internal pull-up resistor on pin 35

allowing it to be either connected to +5V or left open when a

logic "1" is required.

4. To enable the three-state outputs, connect OUTPUT

ENABLE (pin 34) to a logic "0" (low). To disable, connect pin

34 to a logic "1" (high).

5. Applying a start convert pulse while a conversion is in

progress (EOC = logic "1") will initiate a new and probably

inaccurate conversion cycle. Data from both the interrupted

and subsequent conversions will be invalid.

3

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