GS8170LW18C-250I 查看數據表（PDF） - Giga Semiconductor

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GS8170LW18C-250I

18Mb Σ1x1 Late Write SigmaRAM™ SRAM

Giga Semiconductor 

Preliminary

GS8170LW18/36/72C-333/300/250

Read Operations

Flow Through Read

A Flow Through Read cycle sends data to the output drivers immediately after the address and read command are captured in the

input registers. The main clock input, CK, need not ever fire again for data to be driven out. Normally, Flow Through mode is

employed in situations where the latency of the RAM (the Flow Through tKHQV) is appreciably shorter than the bus frequency of

the application. Echo Clock outputs remain high-Z when the RAM is in the Flow Through mode.

Flow Through Read

Read

Deselect

Read

Read

Read

CK

Address

A

XX

C

D

E

F

ADV

/E1

/W

DQ

QA

QC

QD

QE

Key

Hi-Z

Access

Rev: 1.00f 6/2002

10/39

© 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

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