GS8170LW18C-250I 查看數據表（PDF） - Giga Semiconductor

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GS8170LW18C-250I

18Mb Σ1x1 Late Write SigmaRAM™ SRAM

Giga Semiconductor 

209-Bump BGA

Commercial Temp

Industrial Temp

Preliminary

GS8170LW18/36/72C-333/300/250

18Mb Σ1x1 Late Write

SigmaRAM™ SRAM

250 MHz–333 MHz

1.8 V VDD

1.8 V and 1.5 V I/O

Features

• Late Write mode

• User-configurable pipeline and flow through operation

• JEDEC-standard SigmaRAM™ pinout and package

• 1.8 V +150/–100 mV core power supply

• 1.5 V or 1.8 V I/O supply

• Dual Cycle Deselect in Pipeline mode

• Synchronous Burst operation

• Fully coherent read and write pipelines

• Echo Clock outputs track data output drivers in Pipeline

mode

• ZQ mode pin for user-selectable output drive strength

• Byte write operation (9-bit bytes)

• 2 user-programmable chip enable inputs for easy depth

expansion.

• IEEE 1149.1 JTAG-compatible Boundary Scan

• 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package

• Pin-compatible with future 36Mb, 72Mb, and 144Mb devices

Pipeline mode

Flow Through mode

tKHKH

tKHQV

tKHKH

tKHQV

- 333

3.0 ns

1.6 ns

5 ns

5 ns

SigmaRAM Family Overview

GS8170LW18/36/72 SigmaRAMs (ΣRAM™) are built in

compliance with the ΣRAM pinout standard for synchronous

SRAMs. They are 18,874,368-bit (18Mb) SRAMs. These are

the first in a family of wide, very low voltage CMOS I/O

SRAMs designed to operate at the speeds needed to implement

economical high performance networking systems.

GSI's ΣRAMs are offered in a number of configurations that

emulate other synchronous SRAMs, such as Burst RAMs,

NBT, Late Write, or Double Data Rate (DDR) SRAMs. The

logical differences between the protocols employed by these

RAMs hinge mainly on various combinations of address

bursting, output data registering and write cueing. The ΣRAM

family standard allows a user to implement the interface

protocol best suited to the task at hand.

Bottom View

209-Bump, 14 mm x 22 mm BGA

1 mm Bump Pitch, 11 x 19 Bump Array

Functional Description

Because ΣRAMs are synchronous devices, address, data

inputs, and read/write control inputs are captured on the rising

edge of the input clock. Write cycles are internally self-timed

and initiated by the rising edge of the clock input. This feature

eliminates complex off-chip write pulse generation required by

asynchronous SRAMs and simplifies input signal timing.

A ΣRAM may be configured by the user to read in Pipeline or

Flow Through mode. In Pipeline mode, single data rate

ΣRAMs incorporate a rising-edge-triggered output register. For

read cycles, a pipelined SRAM’s output data is staged at the

input of an edge-triggered output register during the access

cycle and then released to the output drivers at the next rising

edge of clock.

GS8170LW18/36/72C ΣRAMs are implemented with GSI's

high performance CMOS technology and are packaged in a

209-bump BGA.

Rev: 1.00f 6/2002

1/39

© 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

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