GS8170LW18C-333 查看數據表（PDF） - Giga Semiconductor

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GS8170LW18C-333

18Mb Σ1x1 Late Write SigmaRAM™ SRAM

Giga Semiconductor 

Preliminary

GS8170LW18/36/72C-333/300/250

Pin Description Table

Pin Location

A3, A5, A7, A9, B7, U4,

U6, U8, V3, V4, V5, V6,

V7, V8, V9, W5, W6, W7

C7

B5

A6

B3, C9

B8, C4

B4, B9, C3, C8

K3

K1, K11

K2, K10

E2, F1, F2, G1, G2, H1,

H2, J1, J2, L10, L11,

M10, M11, N10, N11,

P10, P11, R10

A10, A11, B10, B11,

C10, C11, D10, D11,

E11, R1, T1, T2, U1, U2,

V1, V2, W1, W2

A1, A2, B1, B2, C1, C2,

D1, D2, E1, E10, F10,

F11, G10, G11, H10,

H11, J10, J11, L1, L2,

M1, M2, N1, N2, P1, P2,

R2, R11, T10, T11, U10,

U11, V10, V11, W10,

W11

J6

L6, M6

C6

A4, A8

G6, H6

W9

W4

W8

W3

Symbol

A

A

A

ADV

Bx

Bx

Bx

CK

CQ

CQ

DQ

DQ

DQ

FT

FT

E1

E2 & E3

EP2 & EP3

TCK

TDI

TDO

TMS

Description

Address

Address

Address

Advance

Byte Write Enable

Byte Write Enable

Byte Write Enable

Clock

Echo Clock

Echo Clock

Data I/O

Type

Input

Input

Input

Input

Input

Input

Input

Input

Output

Output

Input/Output

Data I/O

Input/Output

Data I/O

Input/Output

Flow Through or Pipeline mode

Flow Through or Pipeline mode

Chip Enable

Chip Enable

Chip Enable Program Pin

Test Clock

Test Data In

Test Data Out

Test Mode Select

Input

Input

Input

Input

Input

Input

Input

Output

Input

Comments

—

x18 version only

x18 and x36 versions

Active High

Active Low (all versions)

Active Low (x36 and x72 versions)

Active Low (x72 version only)

Active High

Active High

Active Low

x18, x36, and x72 versions

x36 and x72 versions

x72 version only

Active High

Active Low

Active Low

Programmable Active High or Low

—

Active High

—

—

—

Rev: 1.00f 6/2002

5/39

© 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

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