GS818DV18D-250I(2002_11) 查看數據表（PDF） - Giga Semiconductor
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GS818DV18D-250I Datasheet PDF : 26 Pages
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Preliminary
GS818DV18D-333/300/250/200
Pin Description Table
Symbol
SA
NC
R
W
BW0–BW1
Description
Synchronous Address Inputs
No Connect
Synchronous Read
Synchronous Write
Synchronous Byte Writes
Type
Input
—
Input
Input
Input
Comments
—
—
Active Low
Active Low
Active Low
K
Input Clock
K
Input Clock
C
Output Clock
C
Output Clock
TMS
Test Mode Select
TDI
Test Data Input
TCK
Test Clock Input
TDO
Test Data Output
VREF
HSTL Input Reference Voltage
ZQ
Output Impedance Matching Input
MCL
Must Connect Low
CQ
Synchronous Echo Clock Output
CQ
Synchronous Echo Clock-bar Output
D0–D17
Synchronous Data Inputs
Q0–Q17
Synchronous Data Outputs
VDD
Power Supply
VDDQ
Isolated Output Buffer Supply
VSS
Power Supply: Ground
Note: NC = Not Connected to die or any other pin
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
—
Output
Output
Input
Output
Supply
Supply
Supply
Active High
Active Low
Active High
Active Low
—
—
—
—
—
—
—
Echoes C or K Clock
Echoes C or K Clock
—
—
2.5 V Nominal
1.5 V Nominal
—
Background
Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are needed.
Therefore, the SigmaQuad SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O SRAMs are unpopular in
applications where multiple reads or multiple writes are needed because burst read or write transfers from Separate I/O SRAMs can cut the
RAM’s bandwidth in half.
A SigmaQuad SRAM can begin an alternating sequence of reads and writes with either a read or a write. In order for any separate I/O SRAM that
shares a common address between its two ports to keep both ports running all the time, the RAM must implement some sort of burst transfer
protocol. The burst must be at least long enough to cover the time the opposite port is receiving instructions on what to do next. The rate at which
a RAM can accept a new random address is the most fundamental performance metric for the RAM. Each of the three SigmaQuad SRAMs
support similar address rates because random address rate is determined by the internal performance of the RAM and they are all based on the
Rev: 1.01 11/2002
3/26
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
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