GS818DV18D-250I(2002_11) 查看數據表（PDF） - Giga Semiconductor

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GS818DV18D-250I
(Rev.:2002_11)

18Mb Σ2x2B4V SigmaQuad SRAM

Giga Semiconductor 

Preliminary

GS818DV18D-333/300/250/200

same internal circuits. Differences between the truth tables of the different SigmaQuad SRAMs, or any other Separate I/O SRAMs, follow from

differences in how the RAM’s interface is contrived to interact with the rest of the system. Each mode of operation has its own advantages and

disadvantages. The user should consider the nature of the work to be done by the RAM to evaluate which version is best suited to the application

at hand.

Alternating Read-Write Operations

SigmaQuad SRAMs follow a few simple rules of operation.

- Read or Write commands issued on one port are never allowed to interrupt an operation in progress on the other port.

- Read or Write data transfers in progress may not be interrupted and re-started.

- R and W high always deselects the RAM but does not disable the CQ or CQ output pins.

- All address, data, and control inputs are sampled on clock edges.

In order to enforce these rules, each RAM combines present state information with command inputs. See the Truth Table for details.

Rev: 1.01 11/2002

4/26

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

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