ADSP-21375KSZ-ENG 查看數據表（PDF） - Analog Devices

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ADSP-21375KSZ-ENG

SHARC® Processor

Analog Devices 

ADSP-21375

GENERAL DESCRIPTION

The ADSP-21375 SHARC processor is a members of the SIMD

SHARC family of DSPs that feature Analog Devices' Super Har-

vard Architecture. The ADSP-21375 is source code compatible

with the ADSP-2126x, ADSP-2136x, and ADSP-2116x DSPs as

well as with first generation ADSP-2106x SHARC processors in

SISD (single-instruction, single-data) mode. The ADSP-21375

is a 32-bit/40-bit floating point processors optimized for high

performance automotive audio applications with its large on-

chip SRAM and mask-programmable ROM, multiple internal

buses to eliminate I/O bottlenecks, and an innovative digital

applications interface (DAI).

As shown in the functional block diagram on Page 1, the

ADSP-21375 uses two computational units to deliver a signifi-

cant performance increase over the previous SHARC processors

on a range of DSP algorithms. Fabricated in a state-of-the-art,

high speed, CMOS process, the ADSP-21375 processor achieves

an instruction cycle time of 3.75 ns at 266 MHz. With its SIMD

computational hardware, the ADSP-21375 can perform 1.596

GFLOPS running at 266 MHz.

Table 1 shows performance benchmarks for the ADSP-21375.

Table 1. ADSP-21375 Benchmarks (at 266 MHz)

Benchmark Algorithm

Speed

(at 266 MHz)

1024 Point Complex FFT (Radix 4, with reversal) 34.5 μs

FIR Filter (per tap)1

1.88 ns

IIR Filter (per biquad)1

7.5 ns

Matrix Multiply (pipelined)

[3x3] × [3x1]

[4x4] × [4x1]

16.91 ns

30.07 ns

Divide (y/×)

11.27 ns

Inverse Square Root

16.91 ns

1 Assumes two files in multichannel SIMD mode

The ADSP-21375 continues SHARC’s industry leading stan-

dards of integration for DSPs, combining a high performance

32-bit DSP core with integrated, on-chip system features.

The block diagram of the ADSP-21375 on Page 1, illustrates the

following architectural features:

• Two processing elements, each of which comprises an

ALU, multiplier, shifter and data register file

• Data address generators (DAG1, DAG2)

• Program sequencer with instruction cache

• PM and DM buses capable of supporting four 32-bit data

transfers between memory and the core at every core pro-

cessor cycle

• Two programmable interval timers with external event

counter capabilities

• On-chip SRAM (0.5M bit)

Preliminary Technical Data

• On-chip mask-programmable ROM (2M bit)

• JTAG test access port

The block diagram of the ADSP-21375 on Page 1 also illustrates

the following architectural features:

• DMA controller

• Four full duplex serial ports

• Digital applications interface that includes four precision

clock generators (PCG), an input data port (IDP), four

serial ports, eight serial interfaces, a 16-bit parallel input

port (PDAP), and a flexible signal routing unit (DAI SRU).

• Digital peripheral interface that includes two timers, one

UART, two serial peripheral interfaces (SPI), a two wire

interface (TWI), and a flexible signal routing unit (DPI

SRU).

ADSP-21375 FAMILY CORE ARCHITECTURE

The ADSP-21375 is code compatible at the assembly level with

the ADSP-2136x, ADSP-2126x, ADSP-21160 and ADSP-21161,

and with the first generation ADSP-2106x SHARC processors.

The ADSP-21375 shares architectural features with the ADSP-

2126x, ADSP-2136x, and ADSP-2116x SIMD SHARC proces-

sors, as detailed in the following sections.

SIMD Computational Engine

The ADSP-21375 contains two computational processing ele-

ments that operate as a single-instruction multiple-data (SIMD)

engine. The processing elements are referred to as PEX and PEY

and each contains an ALU, multiplier, shifter and register file.

PEX is always active, and PEY may be enabled by setting the

PEYEN mode bit in the MODE1 register. When this mode is

enabled, the same instruction is executed in both processing ele-

ments, but each processing element operates on different data.

This architecture is efficient at executing math intensive DSP

algorithms.

Entering SIMD mode also has an effect on the way data is trans-

ferred between memory and the processing elements. When in

SIMD mode, twice the data bandwidth is required to sustain

computational operation in the processing elements. Because of

this requirement, entering SIMD mode also doubles the band-

width between memory and the processing elements. When

using the DAGs to transfer data in SIMD mode, two data values

are transferred with each access of memory or the register file.

Independent, Parallel Computation Units

Within each processing element is a set of computational units.

The computational units consist of an arithmetic/logic unit

(ALU), multiplier, and shifter. These units perform all opera-

tions in a single cycle. The three units within each processing

element are arranged in parallel, maximizing computational

throughput. Single multifunction instructions execute parallel

ALU and multiplier operations. In SIMD mode, the parallel

ALU and multiplier operations occur in both processing ele-

Rev. PrB | Page 4 of 42 | December 2005

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