ADSP-21375KSZ-ENG 查看數據表（PDF） - Analog Devices

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ADSP-21375KSZ-ENG

SHARC® Processor

Analog Devices 

Preliminary Technical Data

ADSP-21375

The SDRAM controller address, data, clock, and command pins

can drive loads up to 30 pF. For larger memory systems, the

SDRAM controller external buffer timing should be selected

and external buffering should be provided so that the load on

the SDRAM controller pins does not exceed 30 pF.

Table 4. External Memory for SDRAM Addresses

Bank

Bank 0

Bank 1

Bank 2

Bank 3

Size in

words

62M

64M

64M

64M

Address Range

0x0020 0000 – 0x03FF FFFF

0x0400 0000 – 0x07FF FFFF

0x0800 0000 – 0x0BFF FFFF

0x0C00 0000 – 0x0FFF FFFF

Note that the external memory bank addresses shown are for

normal word accesses. If 48-bit instructions are placed in any

such bank (with two instructions packed into three 32-bit loca-

tions), then care must be taken to map data buffers in the same

bank. For example, if 2K instructions are placed starting at the

bank 0 base address (0x0020 0000), then the data buffers can be

placed starting at an address that is offset by 3K words

(0x0020 0C00).

Asynchronous Controller

The asynchronous memory controller provides a configurable

interface for up to four separate banks of memory or I/O

devices. Each bank can be independently programmed with dif-

ferent timing parameters, enabling connection to a wide variety

of memory devices including SRAM, ROM, flash, and EPROM,

as well as I/O devices that interface with standard memory con-

trol lines. Bank0 occupies a 14.7M word window and banks 1, 2,

and 3 occupy a 16M word window in the processor’s address

space but, if not fully populated, these windows are not made

contiguous by the memory controller logic. The banks can also

be configured as 8-bit or 16-bit wide buses for ease of interfac-

ing to a range of memories and I/O devices tailored either to

high performance or to low cost and power.

The asynchronous memory controller is capable of a maximum

throughput of 88M bytes/sec using a 44MHz external bus speed.

Other features include 8 to 32-bit and 16 to 32-bit packing and

unpacking, booting from bank select 1, and support for delay

line DMA.

ADSP-21375 INPUT/OUTPUT FEATURES

The ADSP-21375 I/O processor provides 24 channels of DMA,

as well as an extensive set of peripherals. These include a 20 pin

digital applications interface which controls:

• Four serial ports

• Four precision clock generators

• Internal data port/parallel data acquisition port

The ADSP-21375 processor also contains a 14 pin digital

peripheral interface which controls:

• Two general-purpose timers

• Two serial peripheral interfaces

• One universal asynchronous receiver/transmitter (UART)

• An I2C compatible two wire interface

DMA Controller

The ADSP-21375’s on-chip DMA controller allows data trans-

fers without processor intervention. The DMA controller

operates independently and invisibly to the processor core,

allowing DMA operations to occur while the core is simulta-

neously executing its program instructions. DMA transfers can

occur between the ADSP-21375’s internal memory and its serial

ports, the SPI-compatible (serial peripheral interface) ports, the

IDP (input data port), the parallel data acquisition port (PDAP)

or the UART. Twenty-four channels of DMA are available on

the ADSP-21375—eight via the serial ports, eight via the input

data port, two for the UART, two for the SPI interface, two for

the external port, and two for memory-to-memory transfers.

Programs can be downloaded to the ADSP-21375 using DMA

transfers. Other DMA features include interrupt generation

upon completion of DMA transfers, and DMA chaining for

automatic linked DMA transfers.

Delay Line DMA

The ADSP-21375 processor provides delay line DMA function-

ality. This allows processor reads and writes to external Delay

Line Buffers (and hence to external memory) with limited core

interaction.

Digital Applications Interface (DAI)

The digital applications interface (DAI) provides the ability to

connect various peripherals to any of the DSPs DAI pins

(DAI_P20–1).

Programs make these connections using the signal routing unit

(SRU), shown in Figure 1.

The SRU is a matrix routing unit (or group of multiplexers) that

enables the peripherals provided by the DAI to be intercon-

nected under software control. This allows easy use of the DAI

associated peripherals for a much wider variety of applications

by using a larger set of algorithms than is possible with non con-

figurable signal paths.

The DAI also includes four serial ports, four precision clock

generators (PCG), and an input data port (IDP). The IDP pro-

vides an additional input path to the ADSP-21375 core,

configurable as either eight channels of I2S serial data or as

seven channels plus a single 20-bit wide synchronous parallel

data acquisition port. Each data channel has its own DMA

channel that is independent from the ADSP-21375’s serial ports.

Serial Ports

The ADSP-21375 features four synchronous serial ports that

provide an inexpensive interface to a wide variety of digital and

mixed-signal peripheral devices such as Analog Devices’

AD183x family of audio codecs, ADCs, and DACs. The serial

Rev. PrB | Page 7 of 42 | December 2005

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