ADSP-21MOD870 查看數據表（PDF） - Analog Devices
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ADSP-21MOD870 Datasheet PDF : 32 Pages
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ADSP-21mod870
Reset
The RESET signal initiates a master reset of the ADSP-
21mod870. The RESET signal must be asserted during the
power-up sequence to assure proper initialization. RESET
during initial power-up must be held long enough to allow the
internal clock to stabilize. If RESET is activated any time after
power-up, the clock continues to run and does not require
stabilization time.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid VDD is ap-
plied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum
of 2000 CLKIN cycles ensures that the PLL has locked but
does not include the crystal oscillator start-up time. During
this power-up sequence the RESET signal should be held low.
On any subsequent resets, the RESET signal must meet the
minimum pulsewidth specification, tRSP.
The RESET input contains some hysteresis; however, if you use
an RC circuit to generate your RESET signal, the use of an
external Schmidt trigger is recommended.
The master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts and clears the MSTAT
register. When RESET is released, if there is no pending bus
request and the chip is configured for booting, the boot-loading
sequence is performed. The first instruction is fetched from
on-chip program memory location 0x0000 once boot loading
completes.
MODES OF OPERATION
Table II summarizes the ADSP-21mod870 memory modes.
Setting Memory Mode
The ADSP-21mod870 uses the Mode C pin to make a Memory
Mode selection during chip reset. This pin is multiplexed with
the processor’s PF2 pin, so exercise care when selecting a mode.
The two methods for selecting the value of Mode C are active
and passive.
Passive configuration uses a pull-up or pull-down resistor
connected to the Mode C pin. To minimize power consump-
tion, or if the PF2 pin is used as an output in the DSP applica-
tion, use a weak pull-up or pull-down, on the order of 100 kΩ.
This value should be sufficient to pull the pin to the desired
level and still let the pin operate as a programmable flag output
without undue strain on the processor’s output driver. For mini-
mum power consumption during power-down, reconfigure PF2
as an input, as the pull-up or pull-down will hold the pin in a
known state, and will not switch.
Active configuration uses a three-statable external driver con-
nected to the Mode C pin. A driver’s output enable should be
connected to the processor’s RESET signal so it only drives the
PF2 pin when RESET is active (low). When RESET is de-as-
serted, the driver should three-state, allowing the PF2 pin to be
an input or output. To minimize power consumption during
power-down, configure the programmable flag as an output when
connected to a three-stated buffer. This ensures that the pin is
Table II. Modes of Operation1
MODE D2 MODE C3 MODE B4 MODE A5 Booting Method
X
0
0
0
BDMA feature is used to load the first 32 program memory words from the
byte memory space. Program execution is held off until all 32 words have
been loaded. Chip is configured in Full Memory Mode.6
X
0
1
0
No automatic boot operations occur. Program execution starts at external
memory location 0. Chip is configured in Full Memory Mode. BDMA can
still be used but the processor does not automatically use or wait for these
operations.
0
1
0
0
BDMA feature is used to load the first 32 program memory words from the
byte memory space. Program execution is held off until all 32 words have
been loaded. Chip is configured in Host Mode. IACK has active pull-down.
(REQUIRES ADDITIONAL HARDWARE).
0
1
0
1
IDMA feature is used to load any internal memory as desired. Program ex-
ecution is held off until internal program memory location 0 is written to.
Chip is configured in Host Mode.6 IACK has active pull-down.
1
1
0
0
BDMA feature is used to load the first 32 program memory words from the
byte memory space. Program execution is held off until all 32 words have
been loaded. Chip is configured in Host Mode; IACK requires external pull-
down. (REQUIRES ADDITIONAL HARDWARE).
1
1
0
1
IDMA feature is used to load any internal memory as desired. Program ex-
ecution is held off until internal program memory location 0 is written to.
Chip is configured in Host Mode. IACK requires external pull-down.6
NOTES
1All mode pins are recognized while RESET is active (low).
2When Mode D = 0 and in host mode, IACK is an active, driven signal and cannot be “wire ORed.”
When Mode D = 1 and in host mode, IACK is an open source and requires an external pull-down, multiple IACK pins can be “wire ORed” together.
3When Mode C = 0, Full Memory Mode enabled. When Mode C = 1, Host Memory Mode enabled.
4When Mode B = 0, Auto Booting enabled. When Mode B = 1, no Auto Booting.
5When Mode A = 0, BDMA enabled. When Mode A = 1, IDMA enabled.
6Considered standard operating settings. Using these configurations allows for easier design and better memory management.
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