ADSP-BF523KBCZ-5(RevPrG) 查看數據表（PDF） - Analog Devices
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ADSP-BF523KBCZ-5 Datasheet PDF : 80 Pages
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Preliminary Technical Data
ADSP-BF522/523/524/525/526/527
Deep Sleep Operating Mode—Maximum Dynamic Power
Savings
The deep sleep mode maximizes dynamic power savings by dis-
abling the clocks to the processor core (CCLK) and to all
synchronous peripherals (SCLK). Asynchronous peripherals,
such as the RTC, may still be running but cannot access internal
resources or external memory. This powered-down mode can
only be exited by assertion of the reset interrupt (RESET) or by
an asynchronous interrupt generated by the RTC. When in deep
sleep mode, an RTC asynchronous interrupt causes the proces-
sor to transition to the Active mode. Assertion of RESET while
in deep sleep mode causes the processor to transition to the full
on mode.
Hibernate State—Maximum Static Power Savings
The hibernate state maximizes static power savings by disabling
the voltage and clocks to the processor core (CCLK) and to all of
the synchronous peripherals (SCLK). The internal voltage regu-
lator (ADSP-BF523/525/527 only) for the processor can be shut
off by writing b#00 to the FREQ bits of the VR_CTL register.
This setting sets the internal power supply voltage (VDDINT) to
0 V to provide the lowest static power dissipation. Any critical
information stored internally (for example, memory contents,
register contents, and other information) must be written to a
non-volatile storage device prior to removing power if the pro-
cessor state is to be preserved. Writing b#00 to the FREQ bits
also causes EXT_WAKE0 and EXT_WAKE1 to transition low,
which can be used to signal an external voltage regulator to shut
down.
Since VDDEXT and VDDMEM can still be supplied in this mode, all
of the external pins three-state, unless otherwise specified. This
allows other devices that may be connected to the processor to
still have power applied without drawing unwanted current.
The Ethernet or USB modules can wake up the internal supply
regulator (ADSP-BF525 and ADSP-BF527 only) or signal an
external regulator to wake up using EXT_WAKE0 or
EXT_WAKE1. If PG15 does not connect as a PHYINT signal to
an external PHY device, PG15 can be pulled low by any other
device to wake the processor up. The processor can also be
woken up by a real-time clock wakeup event or by asserting the
RESET pin. All hibernate wakeup events initiate the hardware
reset sequence. Individual sources are enabled by the VR_CTL
register. The EXT_WAKEx signals are provided to indicate the
occurrence of wakeup events.
As long as VDDEXT is applied, the VR_CTL register maintains its
state during hibernation. All other internal registers and memo-
ries, however, lose their content in the hibernate state. State
variables may be held in external SRAM or SDRAM. The SCK-
ELOW bit in the VR_CTL register controls whether or not
SDRAM operates in self-refresh mode, which allows it to retain
its content while the processor is in hibernate and through the
subsequent reset sequence.
Power Savings
As shown in Table 5, the processor supports six different power
domains, which maximizes flexibility while maintaining com-
pliance with industry standards and conventions. By isolating
the internal logic of the processor into its own power domain,
separate from the RTC and other I/O, the processor can take
advantage of dynamic power management without affecting the
RTC or other I/O devices. There are no sequencing require-
ments for the various power domains, but all domains must be
powered according to the appropriate Specifications table for
processor Operating Conditions; even if the feature/peripheral
is not used.
Table 5. Power Domains
Power Domain
VDD Range
All internal logic, except RTC, Memory, USB, OTP VDDINT
RTC internal logic and crystal I/O
VDDRTC
Memory logic
VDDMEM
USB PHY logic
VDDUSB
OTP logic
VDDOTP
All other I/O
VDDEXT
The dynamic power management feature of the processor
allows both the processor’s input voltage (VDDINT) and clock fre-
quency (fCCLK) to be dynamically controlled.
The power dissipated by a processor is largely a function of its
clock frequency and the square of the operating voltage. For
example, reducing the clock frequency by 25% results in a 25%
reduction in dynamic power dissipation, while reducing the
voltage by 25% reduces dynamic power dissipation by more
than 40%. Further, these power savings are additive, in that if
the clock frequency and supply voltage are both reduced, the
power savings can be dramatic, as shown in the following
equations.
Power Savings Factor
=
-f--C----C---L---K---R----E---D--
fCCLKNOM
×
V--V---D-D---D-D--I-I-N-N---T-T--N-R---OE---D-M--
2
×
-T----R----E---D--
TNOM
% Power Savings = (1 – Power Savings Factor) × 100%
where the variables in the equations are:
fCCLKNOM is the nominal core clock frequency
fCCLKRED is the reduced core clock frequency
VDDINTNOM is the nominal internal supply voltage
VDDINTRED is the reduced internal supply voltage
TNOM is the duration running at fCCLKNOM
TRED is the duration running at fCCLKRED
ADSP-BF523/525/527 VOLTAGE REGULATION
The ADSP-BF523/525/527 provides an on-chip voltage regula-
tor that can generate processor core voltage levels from an
external supply. Figure 5 shows the typical external components
required to complete the power management system. The regu-
lator controls the internal logic voltage levels and is
programmable with the voltage regulator control register
(VR_CTL) in increments of 50 mV. To reduce standby power
Rev. PrG | Page 15 of 80 | February 2009
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