ADSP-BF523KBCZ-5(RevPrG) 查看數據表（PDF） - Analog Devices

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ADSP-BF523KBCZ-5
(Rev.:RevPrG)

Blackfin® Embedded Processor

Analog Devices 

ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

The maximum CCLK frequency not only depends on the part's

speed grade (see Page 80), it also depends on the applied VDDINT

voltage. See Table 12 and Table 15 for details. The maximal sys-

tem clock rate (SCLK) depends on the chip package and the

applied VDDINT, VDDEXT, and VDDMEM voltages (see Table 14 and

Table 17).

BOOTING MODES

The processor has several mechanisms (listed in Table 8) for

automatically loading internal and external memory after a

reset. The boot mode is defined by four BMODE input pins

dedicated to this purpose. There are two categories of boot

modes. In master boot modes the processor actively loads data

from parallel or serial memories. In slave boot modes the pro-

cessor receives data from external host devices.

The boot modes listed in Table 8 provide a number of mecha-

nisms for automatically loading the processor’s internal and

external memories after a reset. By default, all boot modes use

the slowest meaningful configuration settings. Default settings

can be altered via the initialization code feature at boot time or

by proper OTP programming at pre-boot time. The BMODE

pins of the reset configuration register, sampled during power-

on resets and software-initiated resets, implement the modes

shown in Table 8.

Table 8. Booting Modes

BMODE3–0 Description

0000

Idle - No boot

0001

Boot from 8- or 16-bit external flash memory

0010

Boot from 16-bit asynchronous FIFO

0011

Boot from serial SPI memory (EEPROM or flash)

0100

Boot from SPI host device

0101

Boot from serial TWI memory (EEPROM/flash)

0110

Boot from TWI host

0111

Boot from UART0 Host

1000

Boot from UART1 Host

1001

Reserved

1010

Boot from SDRAM

1011

Boot from OTP memory

1100

Boot from 8-bit NAND flash

via NFC using PORTF data pins

1101

Boot from 8-bit NAND flash

via NFC using PORTH data pins

1110

Boot from 16-Bit Host DMA

1111

Boot from 8-Bit Host DMA

• Idle/no boot mode (BMODE = 0x0) — In this mode, the

processor goes into idle. The idle boot mode helps recover

from illegal operating modes, such as when the OTP mem-

ory has been misconfigured.

• Boot from 8-bit or 16-bit external flash memory

(BMODE = 0x1) — In this mode, the boot kernel loads the

first block header from address 0x2000 0000, and (depend-

ing on instructions contained in the header) the boot

kernel performs an 8- or 16-bit boot or starts program exe-

cution at the address provided by the header. By default, all

configuration settings are set for the slowest device possible

(3-cycle hold time, 15-cycle R/W access times, 4-cycle

setup).

The ARDY is not enabled by default, but it can be enabled

through OTP programming. Similarly, all interface behav-

ior and timings can be customized through OTP

programming. This includes activation of burst-mode or

page-mode operation. In this mode, all asynchronous

interface signals are enabled at the port muxing level.

• Boot from 16-bit asynchronous FIFO (BMODE = 0x2) —

In this mode, the boot kernel starts booting from address

0x2030 0000. Every 16-bit word that the boot kernel has to

read from the FIFO must be requested by placing a low

pulse on the DMAR1 pin.

• Boot from serial SPI memory, EEPROM or flash

(BMODE = 0x3) — 8-, 16-, 24-, or 32-bit addressable

devices are supported. The processor uses the PG1 GPIO

pin to select a single SPI EEPROM/flash device and sub-

mits a read command and successive address bytes (0x00)

until a valid 8-, 16-, 24-, or 32-bit addressable device is

detected. Pull-up resistors are required on the SPISEL1 and

MISO pins. By default, a value of 0x85 is written to the

SPI_BAUD register.

• Boot from SPI host device (BMODE = 0x4) — The proces-

sor operates in SPI slave mode and is configured to receive

the bytes of the LDR file from an SPI host (master) agent.

The HWAIT signal must be interrogated by the host before

every transmitted byte. A pull-up resistor is required on the

SPISS input. A pull-down on the serial clock (SCK) may

improve signal quality and booting robustness.

• Boot from serial TWI memory, EEPROM/flash

(BMODE = 0x5) — The processor operates in master mode

and selects the TWI slave connected to the TWI with the

unique ID 0xA0.

The processor submits successive read commands to the

memory device starting at internal address 0x0000 and

begins clocking data into the processor. The TWI memory

device should comply with the Philips I2C® Bus Specifica-

tion version 2.1 and should be able to auto-increment its

internal address counter such that the contents of the

memory device can be read sequentially. By default, a

PRESCALE value of 0xA and a TWI_CLKDIV value of

0x0811 are used. Unless altered by OTP settings, an I2C

memory that takes two address bytes is assumed. The

development tools ensure that data booted to memories

that cannot be accessed by the Blackfin core is written to an

intermediate storage location and then copied to the final

destination via memory DMA.

• Boot from TWI host (BMODE = 0x6) — The TWI host

selects the slave with the unique ID 0x5F.

The processor replies with an acknowledgement and the

host then downloads the boot stream. The TWI host agent

should comply with the Philips I2C Bus Specification

Rev. PrG | Page 18 of 80 | February 2009

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